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FAIR1/FAIR2:
Local Arbiter Fairness State Machines
These equations describe two independent state machines which gate the RXRDY1 and RXRDY2 signals in such a way that
they obey the Fairness algorithm. Both machines are contained in a 16L8 PAL. The equations for the transmitter signal state
machines (contained in FAIR2 PAL) are identical to these equations except that the receiver signals are exchanged for corre-
sponding transmitter signals and vice versa.
Outputs: rx1q1, rx1q0, rx2q1, rx2q0, rx1fair, rx2fair: pins 13, 14, 15, 16, 17, 18;
Inputs: rx1, rx2, tx1, tx2, PREEMPT, fair chrst: pins 1, 2, 3, 4, 5, 6, 7;
States:
rx1Ðst
e
[
rx1q1, rx1q0
]
; rx2Ðst
e
[
rx2q1, rx2q0
]
;
rx1Ðidle
e
rx1Ðst
e e
[
1,1
]
;
rx1Ðxfr
e
rx1Ðst
e e
[
1,0
]
;
rx1Ðwait
e
rx1Ðst
e e
[
0,0
]
;
rx1Ðtemp
e
rx1Ðst
e e
[
0,1
]
;
rx2Ðidle
e
rx2Ðst
e e
[
1,1
]
;
rx2Ðxfr
e
rx2Ðst
e e
[
1,0
]
;
rx2Ðwait
e
rx2Ðst
e e
[
0,0
]
;
rx2Ðtemp
e
rx2Ðst
e e
[
0,1
]
;
Equations
!rx1q0
e
rx1Ðidle & rx1 & !chrst
Ý
rx1Ðxfr & rx1 & !chrst
Ý
rx1Ðxfr & !rx1 & fair & !chrst
Ý
rx1Ðwait & fair & !(!rx2 & !tx1 & !tx2 & PREEMPT) & !chrst;
!rx1q1
e
rx1Ðxfr & !rx1 & fair & !chrst
Ý
rx1Ðwait & !(!rx2 & !tx1 & !tx2 & PREEMPT) & !chrst
Ý
rx1Ðwait & !rx2 & !tx1 & !tx2 & PREEMPT & !chrst;
!rx2q0
e
rx2Ðdle & rx2 & !chrst
Ý
rx2Ðxfr & rx2 & !chrst
Ý
rx2Ðxfr & !rx2 & fair !chrst
Ý
rx2Ðwait & fair & !(!rx1 & !tx1 & !tx2 & PREEMPT) & !chrst;
!rx2q1
e
rx2Ðxfr & !rx2 & fair & !chrst
Ý
rx2Ðwait & !(!rx1 & !tx1 & !tx2 & PREEMPT) & !chrst
Ý
rx2Ðwait & !rx1 & !tx1 & !tx2 & PREEMPT & !chrst;
rx1fair
e
!rx1q1;
rx2fair
e
!rx2q1;
Interrupt Logic
This logic provides the interface between the UART and TC interrupts and the IRQ3 and IRQ4 signals on the Micro Channel. It
also provides the Adapter ID bytes in response to ID byte reads. The device used is a 16L8 PAL.
Outputs IRQ3ÐEN, IRQ4ÐEN, IRQ3, IRQ4, bit 7, bit 4 bit 1, bit 0: pins 15, 16, 17, 18, 19, 12, 14, 13;
Inputs: intr1, intr2, P102B2, P102B5, CDEN, RD100, RD101, dmaÐint, RDÐBOTH: pins 1, 2, 3, 4, 5, 6, 7, 8, 9;
Equations
enable IRQ3
e
intr1 & !P102B5 & CDEN
Ý
intr2 & !P102B2 & CDEN
Ý
dmaÐint & CDEN;
enable IRQ4
e
intr1 & P102B5 & CDEN
Ý
intr2 & P102B2 & CDEN;
IRQ3
e
0; IRQ4
e
0
enable bit 7
e
RDÐBOTH;
enable bit 4
e
RDÐBOTH;
enable bit 1
e
!RD100;
enable bit 0
e
!RD101;
bit 7
e
0; bit 4
e
0; bit 1
e
0; bit 0
e
0;
17
Summary of Contents for PC16552C
Page 2: ...PC16552C Adapter Block Diagram TL F 11195 1 2 ...
Page 18: ...TL F 11195 7 18 ...
Page 19: ...TL F 11195 8 19 ...
Page 20: ...TL F 11195 9 20 ...
Page 21: ...TL F 11195 10 21 ...
Page 22: ...TL F 11195 11 22 ...
Page 23: ...TL F 11195 12 23 ...