National Semiconductor PC16552C, Manual

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TL/F/11195 – 3
FIGURE 2. Lockout State Machine
Upon entering a request state, Lockout asserts the DREQ
signal and a 2-bit code, S1 and S0 (not to be confused with
the bus signals S1, S0) corresponding to the request select-
ed. The machine remains in the request state until the cor-
responding request signal goes inactive signifying the end
of the DMA service. It then moves back to the idle state,
deasserts DREQ and waits for a new request.
A delay feature was implemented to handle two or more
requests active at one time. Without this delay, the machine
would move very quickly from a request state, through the
Idle state and into the next highest priority request state.
The result is that the DREQ signal, which is inactive only
while in the Idle state, does not go inactive long enough to
cause a state change in the Busarb state machine (see Lo-
cal Arbiter). BUSARB must change states so that it can sig-
nal the end of a transfer to the DMA controller by deassert-
ing BURST. The Delay input to the Lockout machine is the
feedback DREQ signal, inverted and delayed 100 ns. During
a transfer, DREQ is active low and the Delay signal is active
high. At the end of a transfer cycle, the Lockout machine
moves to the Idle state and deaserts DREQ. It will stay in
Idle until the Delay signal goes inactive low 100 ns later.
Thus DREQ is guaranteed to be inactive for at least 100 ns.
Selection of Arbitration Vector
The PC16552C Adapter is designed to store four different
arbitration vectors which correspond to the 4 DMA channels
programmed to service the UART’s RXRDY and TXRDY
DMA request signals. Two 74LS153 Dual 4-Line to 1-Line
Data selectors are used to present the proper vector to the
Arbcon PAL for arbitration (see Local Arbiter). The S0, S1
outputs of Lockout are connected to the select inputs of the
Data Selectors. The data inputs to the selectors are the
outputs of the POS registers holding the arbitration vectors.
Note, however, that in this design the vector for TXRDY1 is
hardwired to 0111, the lowest priority vector, due to lack of
POS space. Another POS register could have been added
to provide flexibility for the TXRDY1 vector, but would have
required additional logic.
Local Arbiter
The PC16552C Adapter implements the Local Arbiter in two
PALs, Arbcon and Busarb.
The Arbcon 20L8A PAL implements the vector arbitration
function. It competes for the bus with the vector belonging
to the UART request selected by Lockout. The ENARB sig-
nal from the Busarb state machine gates the vector onto the
ARB bus during the arbitration cycle. If the Arbcon logic
finds a match between its vector and the ARB bus, it has
won the bus and signals to the Busarb machine by asserting
BUSWIN.
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