National Semiconductor PC16552C, Manual

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The most important feature of the extended mode is that it
provides access to two new registers: the I/O Address reg-
ister and the Extended Mode register. The programmer can
now use the I/O Address register to specify the address of
the I/O port being serviced (the 8237 and therefore the AT
machines are not capable of generating this address). The
Extended Mode register defines the operation of the chan-
nel: Read Memory or Write Memory, Verify or Transfer data,
8-bit or 16-bit transfers and enable/disable of the I/O ad-
dress generation.
The controller begins the DMA transfers when a DMA slave
has won the arbitration bus and the DMA controller has
been unmasked and programmed to service the winning re-
quest. The controller performs transfers serially with sepa-
rate read and write cycles for each byte or word transferred.
The DMA bus cycles are identical to CPU bus cycles. They
may be Default cycles or be extended by the CHRDY signal.
Driver Programs
Two driver programs are included in this package that dem-
onstrate four simultaneous file transfersÐRXTX.C, which
operates with slave-terminated burst transfers and RXTXI.C,
which uses controller-terminated transfers for the serial
transmitter channels. Both programs are relatively simple
since most of the work is done by the DMA controller, not
the CPU.
RXTX.C
RXTX.C performs the following functions:
Ð allocates 4 RAM buffers the same size as the 4
files being transferred.
Ð initializes the two serial ports to 19.2k, 8, N, 1
and enables the FIFOs and line status registers.
Receiver FIFO trigger levels are set to 14.
Ð programs the following into the DMA controller:
# starting address of the RAM buffers into the
Memory Address registers
#
I/O addresses of the UART receive and trans-
mit FIFOs into the I/O address registers
#
number of bytes in the files into the Terminal
Count registers
# receiver channels’ Extended Mode registers
are set for 8-bit transfers from memory to the
programmed I/O addresses
#
transmit channels’ Extended Mode registers
are set for 8-bit transfers from the pro-
grammed I/O addresses to memory
Ð fills transmit data buffers with 00 – FFh test data
Ð 8259 PIC is programmed to execute dmaÐint()
upon receiving an IRQ3 interrupt
Ð Enables UART DMA request by writing xFh to
DMAÐEN
Ð waits for all file transfers to complete
The DMA channels programmed for the UART requests are:
channel 0ÐRXRDY1; channel 1ÐRXRDY1; channel 6Ð
TXRDY1; channel 7ÐTXRDY1. These numbers correspond
to the arbitration vectors specified in the adapter’s ADF.
Immediately after enabling the UART DMA requests, the
adapter will generate transmit FIFO empty requests
(TXRDY1 and TXRDY2), the controller will service the re-
quests and data will begin transmitting from the UART. One
or two other systems must also begin at this time to transmit
00 – FFh test data to the two receivers. The size of these
files must be the same as the Terminal Count programmed
into the DMA channels servicing the receivers. The receiv-
ers will generate their first request after the first 14 bytes
arrive. The CPU sits in a wait loop while the DMA controller
continues to service the serial ports. The program stops af-
ter all four files have been transferred.
The dmaÐint( ) IRQ3 service routine is executed if a line
status error is generated or a TC is generated by a file trans-
fer completion. The routine first checks for line status errors
in both channels. It then reads the 1-bit Interrupt Status
Register (ISR) which will be set if a TC has occurred. The
program then identifies which of the four file transfers com-
pleted by reading the DMA controller’s status registers.
They contain bit locations for all 8 channels which are set if
a TC has been reached on that channel.
For any channel that has generated a TC, the DMA control-
ler mask bit for that channel is set along with a flag signify-
ing file transfer completion. If a channel servicing a receiver
generated a TC, the received data is also verified by check-
ing the data in the RAM buffer. Finally, RAM buffers are
deallocated.
RXTXII.C
This driver is identical to RXTX.C except that the DMA chan-
nels servicing the UART transmitter FIFOs are programmed
differently and TC interrupts for the transmitters are serv-
iced differently. This is a sample driver for the old version of
the PC16552C which cannot run slave-terminated bursts on
the transmitter.
The DMA channels for the transmit FIFOs are programmed
with a TC of 16 or lessÐnot with the size of the entire file.
This causes the controller to terminate the burst when the
FIFO is full instead of waiting for TXRDY to go inactive
which will be late as discussed in Design Considerations.
During initialization and after every burst transfer to the
transmit FIFOs, the TC is programmed for 16 bytes unless
there are less than that left in the file. A software counter
keeps track of the number of bytes transferred.
dmaÐint() is executed after every service of the FIFO be-
cause of the TC indication. Line Status interrupts and the
receiver channels are treated the same as in RXTX.C.
Transmitter channels are masked, have their TC registers
reloaded
as explained above and then unmasked.
DMAÐEN is written with a special mask variable (chÐcom-
plete) that remembers which DMA channels are no longer in
operation so as not to inadvertantly enable another channel.
EISA BUS DESIGN COMPARISON
From a DMA slave’s point of view, the DMA system in EISA
machines is essentially the same as in ISA machines. DMA
requests from a slave device interface directly to the EISA
bus DRQ signals. No local arbitration is necessary.
An EISA bus design utilizing the PC16552C DMA request
signals would be much simpler than the Micro Channel de-
sign. The RXRDY and TXRDY DMA request signals would
be connected directly to 4 different system DRQ signals,
eliminating the need for the Local Arbiter, Fairness logic,
request selection and lockout, and the generation of 4 arbi-
tration vectors. However it would still be necessary to imple-
ment a DMA request enable register and Terminal Count
handling logic.
The advantage of a DMA slave design for an EISA machine
over an ISA machine is the increased DMA transfer rate.
EISA specifies enhanced DMA modes which will transfer
data at a substantially higher rate than the 4 MHz rate that is
standard on ISA machines.
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