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POS Registers

Address (hex)

Function

0100 (POS Register 100) Adapter Identification Byte (LSB)
0101 (POS Register 101) Adapter Identification Byte (MSB)
0102 (POS Register 102) General Option Select Data
0103 (POS Register 103) General Option Select Data
0104 (POS Register 104) General Option Select Data
0105 (POS Register 105) General Option Select Data
0106 (POS Register 106) Sub Address Extension (LSB)
0107 (POS Register 107) Sub Address Extension (MSB)

Registers 100 and 101 are read-only and registers 102 – 107
are read and write. The ID registers are required on all
adapters, but all bits in registers 102 – 105 are optional and
user-defined except for the following:

102 Bit 0: Card Enable (CDEN): This bit must be imple-
mented and is used to enable the entire adapter card. It
is set last during POS initialization and only if the card will
not produce any resource conflicts. The CDEN signal
gates the decode of all addresses used on the adapter
as well as any interrupt requests.

105 Bit 7: Channel Check Active Indicator. This bit is
required only by adapters which generate CHCK errors
(see Micro Channel Interface Control Signals). Error han-
dlers need this bit to identify the source of the error sig-
nal.

105 Bit 6: Channel Check Status Indicator (STAT). This
bit is also required only by adapters supporting CHCK. It
is used to indicate that channel check status information
is available in POS106 and 107.

PC16552C Serial/DMA Adapter

POS Register Description

The Chips and Technologies 82C611 Micro Channel Inter-
face IC, used to simplify the interface between the
PC16552C Adapter and the Micro Channel, provides good
POS register support. For all 8 POS registers, the 82C611
can be configured to generate read and write strobes for
externally implemented registers or can implement registers
internally. The 82C611 defines how several of the POS bits
used in this adapter were assigned. As can be seen in the
following register descriptions, some bits are available on
external pins while others are used for internal address de-
coding or to define the operating modes of the 82C611.

POS100 and POS101ÐAdapter ID Bytes

All adapters must store a two-byte ID number in POS regis-
ters 100 and 101. IBM specifies that all direct program con-
trol adapters (including memory-mapped I/O) have an ID
byte between 6000 and 6FFFh. As previously mentioned,
the ID byte for this adapter is 6E6DH. When POS100 and
101 are read during setup, the 82C611 produces two sepa-

rate read strobesÐ100RD and 101RD. These signals, as
well as their logical AND, are used by the INTR PAL to pull
down the data bus bits necessary for the CPU to read back
6D from POS100 and 6E from POS101 (see INTR.ABL for
equations). The data bus is pulled up to insure legal high
levels on bits not driven low.

6E6D has been registered at IBM and is guaranteed not to
conflict with any other legitimate adapters. The number to
call to register an ID is 800-426-7763. It is a good idea to
find out what numbers are available before implementing it
in a design as many numbers are already reserved. Num-
bers that minimize the logic necessary to implement them
have as few logic 0 bits as possible and also have low and
high order bytes that have 0 bits in the same position.

POS102

This register is internal to the 82C611 and has all 8 bits
brought out to pins POS102B1 – 7 and CDEN. It is pro-
grammed as follows:

102B7: Fairness: (Used to enable IBM’s
Fairness algorithm. See DMA INTERFACE.)

102B6: A7*A6*A4
102B5: A8
102B4: A3
(Address bits providing decode information
for UART channel 1.)

102B3: A7*A6*A4
102B2: A8
102B1: A3
(Address bits providing decode information
for UART Channel 1.)

102B0: CDEN: (See POS Registers.)

POS103

This register is internal to the 82C611. The bits are not avail-
able on external pins but instead are compared to 3 input
pins which are connected to address bus bits 14, 13 and 12.
A match produces an output used for the decode of the
UART channels.

102B7: unused
102B6: unused

102B5: A14
102B4: A13
102B3: A12
(Address bits providing decode information
for UART channel 1.)

102B2: A14
102B1: A13
102B0: A12
(Address bits providing decode information
for UART channel 2.)