National Semiconductor PC16552C Manual Download

Page: 5 / 24

POS104

This register stores the bus arbitration vectors for the UART
receiver DMA requests RXRDY1 and RXRDY2. It is imple-
mented externally using a 74LS374 latch and 74LS245 buff-
er. The 82C611 decodes reads and writes to the register
during setup and provides the correct strobes. This informa-
tion is also needed as external signals so they were imple-
mented in a register with corresponding output pins.

102B7:

RX2 ARB3

102B6:

RX2 ARB2

102B5:

RX2 ARB1

102B4:

RX2 ARB0

102B3:

RX1 ARB3

102B2:

RX1 ARB2

102B1:

RX1 ARB1

102B0:

RX1 ARB0

POS105

This register is implemented internal to the 82C611. The
lower four bits contain the arbitration vector for UART chan-
nel 1 transmitter. They were selected for the vector because
output pins were needed. The upper four bits contain con-
trol bits for the Micro Channel interface.

105B7: Channel Check Active Indicator. See
POS registers. It is not used in this
adapter.

105B6: Channel Check Status Indicator
(STAT). See POS Registers. It is not used in
this adapter.

105B5: Synchronous Extended Mode: The 82C611
specifies the definition of this bit. It
generates synchronous extended cycles if set
and asynchronous extended cycles if cleared
(see CHRDY in Micro Channel Control
Signals).

105B4: unused

105B3: TX1 ARB3
105B2: TX1 ARB2
105B1: TX1 ARB1
105B0: TX1 ARB0

POS106

and

POS107

are not used in this adapter. The sub-

addressing bits are used to specify the location of a block of
initial program load (IPL) or additional setup information.

MICRO CHANNEL BUS INTERFACE

Micro Channel Control Signals

All of the Micro Channel signals needed to control an 8- or
16-bit adapter are described below. They are all connected
directly to the 82C611 which meets all IBM timing and drive
specifications for those signals.

CD SFDBK: Card Selected Feedback:

This signal must be

driven low by an adapter to acknowledge to the system
when it decodes a specified address. The 82C611 drives
this signal low when the adapter logic asserts the part’s
CDSEL input. The CDSEL signal is generated by a logical
OR of the unlatched address decodes of both UART chan-
nels and the two registers decoded on the adapter for DMA
control and status (see DMA Interface Design).

CD DS16: Card Data Size 16:

This signal is driven low

when an adapter requires a 16-bit data transfer. The
82C611 drives this signal as a function of its DS16 input
which is tied high in this design.

CD CHRDY: Card Channel Ready:

An adapter which

needs more time to transfer data on the Micro Channel pulls
this signal low (not ready) to extend the current bus cycle.
There are two types of extended cycles: Asynchronous Ex-
tended and Synchronous Extended. The difference be-
tween them is when the CD CHRDY signal driven back high
(ready). In the synchronous case, CD CHRDY is removed
within 30 ns of the falling edge of CMD. This causes the
system to extend the cycle 100 ns or 1 wait state. In the
asynchronous case, CD CHRDY is removed at any time by
the adapter providing as many wait states as necessary (the
limit for holding CD CHRDY low is 3

s). POS105 bit 5 de-

fines which type the 82C611 supports. A single wait state is
needed to support DMA transfers from the PC16552C so
the bit is programmed for synchronous mode. The 82C611
causes an extended cycle when its ADPRDY signal is as-
serted by the adapter. In this design, the ADPRDY signal is
the same as the CDSEL signal thus causing an extended
cycle to be generated on every access to the Adapter.

CHRESET: Channel Reset:

This active high strobe from

the Micro Channel resets devices on adapter cards. It is
connected to the 82C611, PC16552C, and the Busarb,
Lockout and Fair state machines.

CD SETUP: Card Setup:

The Micro Channel drives this sig-

nal low during POS setup. Upon receiving this signal, the
82C611 places the PC16552C Adapter into setup mode by
allowing access to the POS registers.

REFRESH:

This system indicates through this signal that a

refresh cycle is occuring on the bus. The refresh cycle looks
like a normal memory read, which the 82C611 will ignore
upon receiving an active REFRESH signal.

CHCK: Channel Check:

Adapters assert this signal to indi-

cate a serious error (such as parity) which threatens system
operation. The signal is common to all adapter slots so it
must be driven with an open-collector driver. The 82C611
drives this signal as a function of the ERROR input which is
tied high (inactive) in this design.

S0,S1,M/IO and CMD:

The 82C611 decodes these signals

into separate I/O read (IOR) and I/O write (IOW) strobes.

Data Bus

A 74LS245 buffer isolates the Adapter’s data bus from the
Micro Channel data bus to prevent excessive loading of Mi-
cro Channel bus. Direction and gating during read and write
cycles is controlled by the 82C611’s BUFDIR and BUFENL
signals. The internal bus connects to the PC16552C,
POS104, DMAÐEN and ISR registers (see DMA Interface)

and the INTR PAL (POS ID generator).