National Semiconductor PC16552C Page 18 Manual Download | Manualshive

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Summary of Contents for PC16552C

Page 1: ...sis for a high performance serial port design Advancing modem technology is causing a substantial in crease in serial transfer baud rates putting a severe strain on existing serial port designs Personal computer systems are unable to keep up with transfer rates that are now reaching 115k baud The PC16552C allows the serial port designer to design ports that can handle these faster data rates Trans...

Page 2: ...PC16552C Adapter Block Diagram TL F 11195 1 2 ...

Page 3: ...niz es as an empty slot Since the system remembers which adapter and ID resides in each slot removing a card inserting a new card or even moving an existing card to a different slot will cause a POST failure IBM s System Configuration utilities must then be run to reconfigure the system by modifying the configuration data stored in CMOS RAM ADFsÐAdapter Description Files System board and adapter P...

Page 4: ...n external pins while others are used for internal address de coding or to define the operating modes of the 82C611 POS100 and POS101ÐAdapter ID Bytes All adapters must store a two byte ID number in POS regis ters 100 and 101 IBM specifies that all direct program con trol adapters including memory mapped I O have an ID byte between 6000 and 6FFFh As previously mentioned the ID byte for this adapte...

Page 5: ...ts DS16 input which is tied high in this design CD CHRDY Card Channel Ready An adapter which needs more time to transfer data on the Micro Channel pulls this signal low not ready to extend the current bus cycle There are two types of extended cycles Asynchronous Ex tended and Synchronous Extended The difference be tween them is when the CD CHRDY signal driven back high ready In the synchronous cas...

Page 6: ...d directly to each comparator and compared to POS102 bit 4 and bit 1 which are programmed for channel 1 and channel 2 respectively A14 A13 and A12 are connected to 82C611 multi function pins MFP6 5 and 4 respectively They are constantly com pared to two bit fields in POS103ÐB5 3 and B2 0 Bits 5 3 are programmed with the A14 A13 and A12 bits expected for channel 1 and bits 2 0 with the bits expecte...

Page 7: ...driving the BURST signal until all transfers are complete A bursting device may also stop transfers if another device drives PREEMPT active thus postponing any further transfers until it wins the system channel again IBMÉ requires a bursting device not to ignore an active PREEMPT for more than 7 8 ms thus 7 8 ms is the maxi mum time allowed for a single BURST transfer At this time the Central Arbi...

Page 8: ...ned with the latter implementa tion One particular timing specification required by the Micro Channel when a DMA slave terminates a burst cycle is the most critical issue in the design of a useful DMA serviced serial port The goal of the DMA interface design is to be able to transfer four files simultaneously in two directions with attention from the CPU only at the beginning and end of the file t...

Page 9: ...out a wait state and ran I O read DMA transfers without errors A test of the IO write transfers was futile because only the older PC16552C was available making slave terminated transfers impossible The design chosen for implementation uses just one Local Arbiter and prioritizes the UART DMA requests on the adapter This design was chosen because it is more inform ative example and has a lower chip ...

Page 10: ... stay in Idle until the Delay signal goes inactive low 100 ns later Thus DREQ is guaranteed to be inactive for at least 100 ns Selection of Arbitration Vector The PC16552C Adapter is designed to store four different arbitration vectors which correspond to the 4 DMA channels programmed to service the UART s RXRDY and TXRDY DMA request signals Two 74LS153 Dual 4 Line to 1 Line Data selectors are use...

Page 11: ...s asserted and DMA controller begins transfer XFR3 DREQ has gone inactive signifying completion of transfer BURST is deasserted This is an intermedi ate state to IDLE Fairness IBM s Fairness algorithm is enabled when POS register 102 bit 7 is set An asynchronous state machine for each of the four UART DMA request signals implemented in 2 PALs Fair1 and Fair2 ensures that the four requests obey the...

Page 12: ...he CL in puts of the DMAÐEN register s 74LS74 latches The TC pulse clears the adapter card enable bit for the decoded channel and prevents any further DMA request from that channel until the CPU has re intialized the system for a new file transfer All four UART TC pulses are OR ed together to set a 1 bit read only register called Interrupt Status Register ISR The output of ISR is connected to the ...

Page 13: ...PU sits in a wait loop while the DMA controller continues to service the serial ports The program stops af ter all four files have been transferred The dmaÐint IRQ3 service routine is executed if a line status error is generated or a TC is generated by a file trans fer completion The routine first checks for line status errors in both channels It then reads the 1 bit Interrupt Status Register ISR ...

Page 14: ...oice SERIAL 3 pos 0 4XXXX100Xb pos 1 4XXXXX011b io 3220h 3227h int 3 choice SERIAL 4 pos 0 4XXXX101Xb pos 1 4XXXXX011b io 3228h 322fh int 3 choice SERIAL 5 pos 0 4XXXX100Xb pos 1 4XXXXX100b io 4220h 4227h int 3 choice SERIAL 6 pos 0 4XXXX101Xb pos 1 4XXXXX100b io 4228h 422fh int 3 choice SERIAL 7 pos 0 4XXXX100Xb pos 1 4XXXXX101b io 5220h 5227h int 3 choice SERIAL 8 pos 0 4XXXX101Xb pos 1 4XXXXX10...

Page 15: ...s BUSARB Local Arbiter State Machine The following asynchronous state machine controls the Local Arbiter on the Adapter Card The device used is a 20L8 PAL outputs q3 q2 q1 q0 burst preout ack enarb pins 21 20 19 18 17 16 22 15 inputs dreq arbgnt buswin prein chrst pins 1 2 3 4 5 States of Arbiter idle e 1 1 1 1 req e 1 1 1 0 req uchannel bus preout q0 active arb e 1 0 1 0 vector enabled preout ena...

Page 16: ...nd enarb enable arb3 e sel3 enarb enable arb2 e sel2 Q enarb enable arb1 e sel1 Q2 enarb enable arb0 e sel0 Q2 Q3 enarb LOCKOUT Device Request Lockout State Machine This machine selects and prioritizes the four UART DMA requests and issues a single request to the Local Arbiter Once a particular request is selected all others are locked out The device used is 16L8D PAL Outputs dreq s1 s0 q0 q1 q2 q...

Page 17: ...r rx1 fair chrst Ý rx1Ðwait fair rx2 tx1 tx2 PREEMPT chrst rx1q1 e rx1Ðxfr rx1 fair chrst Ý rx1Ðwait rx2 tx1 tx2 PREEMPT chrst Ý rx1Ðwait rx2 tx1 tx2 PREEMPT chrst rx2q0 e rx2Ðdle rx2 chrst Ý rx2Ðxfr rx2 chrst Ý rx2Ðxfr rx2 fair chrst Ý rx2Ðwait fair rx1 tx1 tx2 PREEMPT chrst rx2q1 e rx2Ðxfr rx2 fair chrst Ý rx2Ðwait rx1 tx1 tx2 PREEMPT chrst Ý rx2Ðwait rx1 tx1 tx2 PREEMPT chrst rx1fair e rx1q1 rx...

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Page 24: ...onal Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd Hong Kong Ltd Do Brazil Ltda Australia Pty Ltd 2900 Semiconductor Drive Livry Gargan Str 10 Sumitomo Chemical 13th Floor Straight Block Rue Deputado Lacorda Franco Building 16 P O Box 58090 D 82256 F4urstenfeldbruck Engineering Center Ocean Centre 5 Canton Rd 120 3A Business Park Dr...

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