National Semiconductor PC16552C, Manual

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Address Decode
Micro Channel adapters should have their resources relo-
catable and selectable through the POS mechanism. This
design allows for the two serial channels on board the
PC16552C to be located at any two of the 8 ‘‘standard’’ IBM
serial port addresses. The following table shows those ad-
dresses:
COM Port Hex Address Binary Address (A15 – 0)
1 03F8 0000 0011 1111 1000
2 02F8 0000 0010 1111 1000
3 3220 0011 0010 0010 0000
4 3228 0011 0010 0010 1000
5 4220 0100 0010 0010 0000
6 4228 0100 0010 0010 1000
7 5220 0101 0010 0010 0000
8 5228 0101 0010 0010 1000
The upper 13 bits of the address must be decoded while the
lower 3 bits, A2 – A0, connect directly to the PC16552C to
select one of 8 internal registers of the selected channel. As
can be seen from the binary addresses above, 5 bits stay
the same for the 8 COM ports (A15, A11, A10, A9, A5) and
8 bits must be programmed for the port selected for decode.
Adapter card logic gates ‘‘compress’’ bit fields that are al-
ways at the same logic level so that all 13 bits will not need
to be decoded separately. The 82C611 has inadequate ad-
dress decoding resources so two 74LS521 Comparators,
one for each UART channel, are implemented to compare
compressed bits and some of the address bus bits with POS
programmed bits and hard-wired bits. POS registers 102
and 103 are programmed with the data necessary to de-
code the two ports selected for use on the adapter (see
POS Register Description). The entire decode works as fol-
lows:
Address bits A15, A11 and A10 are always 0. They are com-
pressed to one bit with a NOR gate and compared to a
hard-wired 1 on both comparators.
A9 and A5 are always 1. They are compressed by a NAND
gate to a bit which is compared to a hard-wired 0 by both
comparators.
A7, A6 and A4 are all 0 if the port address is for COM3 – 8. A
NAND gate compresses the bits to a signal which is com-
pared to POS102 bit 6 by the channel 1 comparator and to
POS102 bit 3 by the channel 2 comparator. Thus POS102
bit 6 must be programmed to a 0 if channel 1 is to be COM1
or COM2 and to a 1 if it’s to be COM3 – 8. POS102 bit 3 is
programmed similarly for channel 2.
A8 is a 1 in the COM1 address and 0 in all others. It is
connected directly to both comparators and compared to
POS102 bit 5 and POS102 bit 2 which are programmed for
channel 1 and channel 2 respectively.
A3 equals 1 in COM1, 2, 4, 6 and 8 and equals 0 in COM3, 5
and 7. It is also connected directly to each comparator and
compared to POS102 bit 4 and bit 1 which are programmed
for channel 1 and channel 2 respectively.
A14, A13 and A12 are connected to 82C611 multi-function
pins MFP6, 5 and 4 respectively. They are constantly com-
pared to two bit fields in POS103ÐB5 – 3 and B2 – 0. Bits 5 –
3 are programmed with the A14, A13 and A12 bits expected
for channel 1 and bits 2 – 0 with the bits expected for chan-
nel 2. The 82C611 will assert MFP3 when a match is made
for channel 1 and will assert MFP2 when a match is made
for channel 2. MFP3 is connected to the channel 1 compar-
ator and MFP2 is connected to the channel 2 comparator.
Both are compared to a hard-wired 0.
As stated in the POS Register Description, POS102 bit 0 is
the card enable signal CDEN. The signal enables UART
address decode by being compared to a hard-wired 1 on
both comparators (CDEN is 0 until POS102 bit 0 is set).
Finally, the M/IO signal from the Micro Channel is used to
gate both LS521 comparators so that only I/O addresses
are decoded. The two comparators produce active low out-
puts when an address match is found. These signals are
CS1 and CS2, the selects for the PC16552’s two channels.
The adapter decodes one additional I/O address, 2F7h,
which is the location of the write-only DMAÐEN register
and read-only ISR register (see DMA Interface for register
description). These registers are not relocatable. However,
the I/O resource is ‘‘claimed’’ in the adapter’s ADF so any
conflict with other cards will be caught by POST which will
not enable the card, preventing system damage.
UART Interface
The PC16552C register address bits (A2, A1, A0) and the
CS outputs of the LS521 comparators are latched into a
74LS373 by the CMD signal and held for the duration of a
bus cycle. The latched CS1 and CS2 signals are ANDed to
produce the PC16552’s CS signal. The correct channel on
the UART is selected by connecting the CS2 signal to the
UART’s CHSL input which produces the following channel
decode:
CS1 CS2 (CHSL) Channel Selected
0 1 1
1 0 2
1 1 X
The adapter’s address decode logic and the PC16552C cy-
cle time is fast enough to operate with the Micro Channel’s
default bus cycle length. No wait states are needed for ac-
cess to the UART.
Interrupts
The Micro Channel’s IRQ interrupts are designed as active-
low, level-sensitive signals. This simplifies adapter interrupt
sharing logic and reduces transient sensitivity on the inter-
rupt controller while retaining compatibility with existing soft-
ware. Because IRQ lines are shared, open-collector drivers
or active-low TRI-STATE
É
drivers must be used by adapters
to drive the lines.
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