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Chapter 5
Programming the High-Speed Serial Ports
•
If you generate an asynchronous reset within your CLIP VHDL, create a false path
constraint from the register that generates the reset signal. Include a “don’t touch” attribute
for any false path constraints.
–
The following is an example syntax for the “don’t touch” attribute:
attribute
dont_touch : string; attribute dont_touch of <signal name> :
signal is "true";
–
The following is an example syntax for the false path constraint:
set_false_path
-from [get_cells %ClipInstancePath%/<path to your register>]
•
When writing constraints, you may need to refer to the CLIP’s instance name or the
absolute path to the CLIP instance in the VHDL hierarchy. Refer to the
or more information about using the search-and-replace keywords
%ClipInstanceName%
and
%ClipInstancePath%
.
Constraints and Hierarchy
You can include CLIP-specific user constraints in the compilation using a constraints file,
depending on your specific FPGA target. You can use this mechanism for all constraints except
pin placement constraints. For example, you can access a clock directly from a global clock input
pin through a global clock buffer for socketed CLIP. You must constrain the period of this clock.
For constraints on specific components within CLIP, you might need to specify the location of
the component within the overall VHDL hierarchy. In such cases, consider prefacing the
constraints with the following macros. Prefacing allows the constraints to be applied regardless
of the component location in the VHDL hierarchy. If you want to use this example code, copy
the code to a text file and save the file as
DemoClipAdder.xdc
. Add this constraints file along
with the VHD file as synthesis files in the Configuring CLIP wizard to implement this constraint.
Xilinx Vivado
create_clock -period 10.000 -name %ClipInstanceName%Clk -waveform
{0.000 5.000} -add [get_pins %ClipInstancePath%/clk]
set_clock_latency -clock [get_clocks {%ClipInstanceName%CLK}] 10.0
[get_pins {%ClipInstancePath%/cAddOut[0]}]
To instantiate the CLIP multiple times, each CLIP instance must have a unique name, and the
name must follow VHDL naming conventions. When you include these macros, you do not need
to include a separate constraints file for each instance because the FPGA Module creates a
unique instance name.
If a CLIP signal is not used, the Xilinx compilation tools might remove the signal from the
bitstream. In such cases, you might get an NGBuild error during compilation. To resolve this
issue, remove the constraint or use the signal in an FPGA VI.
Caution
In order to guarantee data integrity and timing closure, verify that I/O
nodes from the CLIP are written in the same clock domain in which they are read on
the LabVIEW diagram and that I/O nodes to the CLIP are read in the same clock
