© National Instruments
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domain in which they are written on the LabVIEW diagram. In rare cases where
crossing clock domains is desirable, refer to KnowledgeBase
6OB8E8FM
at
ni.com/kb
for more information about how to write timing constraints between the
CLIP and the LabVIEW diagram in order to specify timing exceptions on these paths
and achieve timing closure. Note that data corruption might still occur when crossing
clock domains.
Documenting Your IP
NI recommends documenting the behavior of your CLIP. Refer to the following guidelines for
information about how to document your CLIP and how documenting your CLIP can affect the
rest of your design:
•
Document the endianness of your CLIP in order to properly interface your CLIP to the
LabVIEW FPGA diagram. Refer to the
Writing a VHDL Wrapper Around the Protocol IP
section of this chapter for more information about how CLIP endianness affects the
design process.
•
Clearly define the portion of your entity interface that is facing the diagram, and which
portion of your entity is facing the front panel.
•
Document the connector signals by describing which signals are used, which signals are
unused, and the manner in which the signal is used. Signal use can affect which ports are
active with your IP and the behavior of cables upon ingestion and removal.
•
Document how you integrate AXI4-Lite signals with LabVIEW data types. Some
AXI4-Lite signals do not integrate easily with LabVIEW data types; for example, address
ports can have widths of 11, but LabVIEW only provides addresses with widths of 8, 16,
32, and 64. Additionally, the AXI4-Lite and AXI4-Stream adapters are configured for use
with fixed-point I/O.
•
Document how clocks are used and how they are routed in your CLIP for use with the IP.
You must route clocks to the diagram for use with the single-cycle timed loop (SCTL) in
LabVIEW FPGA.
•
Document the address map of individual components within any AXI4-Lite interfaces.
Adding MGT Socketed CLIP to the LabVIEW
Project
After configuring the MGT Socketed CLIP in VHDL, you can use LabVIEW FPGA to continue
the development process. LabVIEW FPGA provides FPGA target support, configuration for
clocking and routing, and interfacing with LabVIEW on your host computer for a fully
integrated development experience.
Refer to the
section of this manual for a list of LabVIEW FPGA
documentation that you may find helpful as you develop your application.
