© National Instruments
|
5-5
Note
Do not modify the IP core unless you understand the required reference
clock(s) and clocking resources.
The following figure shows the difference between the top-level CLIP VHDL with shared logic
in the core (left) and without shared logic (right).
Figure 5-4.
Top-Level CLIP VHDL and Shared Logic
Building a Netlist from the IP Core
LabVIEW FPGA does not support Verilog source files in Component Level IP. However, you
can generate EDIF netlists from any synthesized Verilog components in the IP you’re using and
instantiate the netlist in a VHDL wrapper.The following steps are an example of how to generate
an EDIF netlist from the IP core:
1.
Open the example project for your IP core in Vivado.
2.
Set the appropriate top-level source file for which you plan to generate a netlist.
3.
Run synthesis.
4.
Open the Synthesized Design using one of the following methods.
•
Select
Open Synthesized Design
in the
Synthesis Completed
pop-up window.
•
Select the
Design Run
tab, then select
Open Synthesized Design
in the left hand
pane.
5.
In the Tcl Console, enter
write_edif <name of entity>.edf
to create the netlist
that you use when you import the IP core into your LabVIEW project. The netlist location
is indicated by the Tcl Console window.
IP Core WITHOUT
S
h
a
red Logic
IP Core WITHOUT
S
h
a
red Logic
Top Level CLIP VHDL
Top Level CLIP VHDL
MGT_RefClk
MGT_RefClk
IBUFD
S
_GTE2
IBUFD
S
_GTE2
IBUFD
S
_GTE2
IP Core WITH
S
h
a
red Logic
IP Core WITH
S
h
a
red Logic
?
