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Basic Elements Overview
This instrument design library contains several low-level elements, such as edge detectors,
latches, and FIFOs. Using this library can be beneficial when developing new FPGA logic for
your software-designed instrument. These basic elements are used in other instrument design
libraries and the sample projects for your device.
Memory Overview
Use the Memory instrument design library to access DRAM and BRAM on the device in a
consistent manner. This library provides a basic read and write interface to DRAM and BRAM.
In addition to the basic memory interface, you can use this instrument design library to reset the
DRAM or BRAM. When memory read operations are posted to memory, there is some amount
of latency before the associated data is retrieved from memory and presented to the FPGA
diagram. Furthermore, multiple read operations can be queued up at once. You can use the
Memory instrument design library to reset those queued memory operations.
This instrument design library also adds support for arbitration between the read and write ports
of DRAM.
Compiling LabVIEW FPGA VIs
You may need to purchase and install additional licenses to compile FPGA designs that
incorporate licensed cores from Xilinx or third-party IP vendors. Refer to
UG 973: Vivado
Design Suite: Release Notes, Installation, and Licensing
at
xilinx.com
for information about
managing licenses.
The NI-793xR targets include large FPGA devices that require a 64-bit compile worker. Refer
to the
FlexRIO Support Readme
for more information about what platforms to use to compile
bitfiles.
You cannot add additional licenses to remote compile workers in the NI LabVIEW FPGA
Compile Cloud Service. You cannot use NI LabVIEW FPGA Compile Cloud Service to compile
designs that incorporate Xilinx or other third-party licensed cores.
Download, Reset, and Run Side Effects in the
LabVIEW FPGA Host Interface
When the NI-793xR FPGA loads, it performs a power-on self-configuration sequence that
configures various on-board hardware. This configuration occurs at the following times:
•
At device power-up after the bitfile loads.
•
At the first time
Run
is called after a new bitfile is downloaded and the bitfile is not set to
Run on Load
.
•
When
Run
is called after
Reset
.
