National Instruments FlexRIO NI-7931R User Manual Download

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5-6

ni.com

Chapter 5

Programming the High-Speed Serial Ports

The following figure shows the cells associated with the design in the

Netlist

window.

To build

.edf

files for an associated cell, enter the following command:

write_edif -cell <name of cell> <file name>.edf

For example, to create an

.edf

for

clock_module_i

, enter the following command:

write_edif -cell clock_module_i

aurora_64b66b_clock_module.edf

Note

You may have to specify a longer path name depending on the location of the

cell in your project. For example, clock_module_i may be located under

aurora_64b66b_0_block_i/clock_module_i

Copy the netlist into your LabVIEW FPGA CLIP directory.

Include your netlist in the list of synthesis files when running the CLIP Wizard.

Summary of Contents for FlexRIO NI-7931R

Page 1: ...NI 7932...

Page 2: ...FlexRIO TM NI 7931R 7932R 7935R User Manual NI 793xR User Manual August 2015 375181B 01...

Page 3: ...ers email addresses and current events National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 For further support information refer to th...

Page 4: ...ESS FOR A PARTICULAR PURPOSE TITLE OR NON INFRINGEMENT AND ANY WARRANTIES THAT MAY ARISE FROM USAGE OF TRADE OR COURSE OF DEALING NI DOES NOT WARRANT GUARANTEE OR MAKE ANY REPRESENTATIONS REGARDING TH...

Page 5: ...es independent from National Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products technology re...

Page 6: ...e encouraged to try to correct the interference by one or more of the following measures Reorient the antenna of the receiver the device suffering interference Relocate the transmitter the device gene...

Page 7: ...5 NI 7932R 3 6 NI 7932R Key Features 3 9 Clocking Architecture 3 11 NI 7935R 3 12 NI 7935R Key Features 3 15 Clocking Architecture 3 16 Chapter 4 Developing with LabVIEW FPGA Developing with LabVIEW F...

Page 8: ...Core 5 7 Constraints and Hierarchy 5 8 Documenting Your IP 5 9 Adding MGT Socketed CLIP to the LabVIEW Project 5 9 Configuring MGT Socketed CLIP in the NI 793xR LabVIEW FPGA Targets 5 10 Using Existin...

Page 9: ...NI 793xR User Manual National Instruments ix Appendix A CLIP Signals Appendix B Using the Fan Appendix C NI Services Glossary...

Page 10: ...guide for your controller for FlexRIO Available from the Start menu Start All Programs National Instruments NI FlexRIO and at ni com manuals Contains information about installing configuring and trou...

Page 11: ...ll Programs National Instruments LabVIEW 201x LabVIEW 201x Help or by searching for Real Time Module Help at ni com manuals Browse to the Real Time Module book in the Contents tab for information abou...

Page 12: ...t DC and AC Switching Characteristics DS182 Contains the DC and AC switching characteristic specifications for the Kintex 7 FPGAs Vivado Design Suite Release Notes Installation and Licensing UG973 Pro...

Page 13: ...s DOC 15799 The FlexRIO Instrument Development Library is a set of host and FPGA code that provides FPGA capabilities commonly found in instruments such as acquisition engines DRAM interfaces and trig...

Page 14: ...fundamentals required for NI 793xR development Table 1 1 Fundamentals Resources Concept Resources Real time programming Real time programming courses are available at ni com training You can also ref...

Page 15: ...m Chapter 1 Before You Begin Xilinx Licensing Information Refer to the Xilinx Documentation section of About This Manual for a list of Xilinx documentation that contains important Xilinx licensing inf...

Page 16: ...er Caution The NI 793xR mounting orientation is not restricted however when mounting the NI 793xR upside down ensure that the FlexRIO adapter module is supported if you expect shock greater than 30 g...

Page 17: ...Before using any of these mounting methods record the serial number from the back of the device You will be unable to read the serial number from the back of the device after you have mounted it Caut...

Page 18: ...e following items to mount the device directly on a flat surface Three screws M4 7 mm thickness of mounting surface Complete the following steps to mount the device 1 Use the dimensions shown in Figur...

Page 19: ...th optional rubber feet Install the rubber feet to the bottom of the device as shown in Figure 2 3 Caution Do not install rubber feet when directly mounting the NI 793xR The rubber feet will prevent f...

Page 20: ...ont panel connectors refer to your device s specifications document and the FlexRIO Help For information about connecting the device to a host computer refer to the NI 7931R Getting Started Guide Figu...

Page 21: ...3 2 ni com Chapter 3 Hardware Architecture The following figure shows the NI 7931R LEDs in more detail Figure 3 2 NI 7931R LEDs RT User LED Power LED Status LED FPGA User LED...

Page 22: ..._34_n GPIO_34 GND GPIO_35_n GPIO_35 GND GPIO_36_n GPIO_36 GND GPIO_37_n GPIO_37 GND GND PCB Secondary Side Bank 0 PCB Primary Side GND GPIO_CC_14_n GPIO_CC_14 GND GPIO_15_n GPIO_15 GND GPIO_16_n GPIO_...

Page 23: ...ocessor to USB external storage data transfer rates of 60 MB s Real Time processor to SD external storage data transfer rates of 12 0 MB s read 9 0 MB s write The following figure illustrates the key...

Page 24: ...locks with LabVIEW FPGA The NI 7931R clocking architecture includes the following clocks 10 MHz Reference Clock 40 MHz Onboard Clock default 100 MHz Clock 200 MHz Clock DRAM Clock The following figure...

Page 25: ...require calibration The following figure shows the NI 7932R front panel connectors For more information about the front panel connectors refer to your device s specifications document and the FlexRIO...

Page 26: ...National Instruments 3 7 NI 793xR User Manual The following figure shows the NI 7932R LEDs in more detail Figure 3 7 NI 7932R LEDs RT User LED Power LED Status LED FPGA User LED...

Page 27: ...4_n GPIO_34 GND GPIO_35_n GPIO_35 GND GPIO_36_n GPIO_36 GND GPIO_37_n GPIO_37 GND GND PCB Secondary Side Bank 0 PCB Primary Side GND GPIO_CC_14_n GPIO_CC_14 GND GPIO_15_n GPIO_15 GND GPIO_16_n GPIO_16...

Page 28: ...s of 3 125 Gbps 6 25 Gbps and 10 3125 Gbps Kintex 7 XC7K325T FPGA 2 GB onboard FPGA accessible DRAM NI Linux Real Time 32 bit controller FPGA to host data transfer rates of 200 MB s single direction 1...

Page 29: ...32R Architecture Key Components RT Host RT Controller RAM NV Storage RT Clock Watch Dog LabVIEW Host VI Interrupts DMA Controls Indicators NI Defined Bus Interfaces Streaming IP Memory Controller DRAM...

Page 30: ...cks 10 MHz Reference Clock 40 MHz Onboard Clock default 100 MHz Clock 156 25 MHz Clock 312 5 MHz MGT Clock1 200 MHz Clock DRAM Clock The following figure illustrates the clocking circuitry on the NI 7...

Page 31: ...equire calibration The following figure shows the NI 7935R front panel connectors For more information about the front panel connectors refer to your device s specifications document and the FlexRIO H...

Page 32: ...National Instruments 3 13 NI 793xR User Manual The following figure shows the NI 7935R LEDs in more detail Figure 3 12 NI 7935R LEDs RT User LED Power LED Status LED FPGA User LED...

Page 33: ...34_n GPIO_34 GND GPIO_35_n GPIO_35 GND GPIO_36_n GPIO_36 GND GPIO_37_n GPIO_37 GND GND PCB Secondary Side Bank 0 PCB Primary Side GND GPIO_CC_14_n GPIO_CC_14 GND GPIO_15_n GPIO_15 GND GPIO_16_n GPIO_1...

Page 34: ...bidirectional Real Time processor to USB external storage data transfer rates of 60 MB s Real Time processor to SD external storage data transfer rates of 12 0 MB s read 9 0 MB s write The following f...

Page 35: ...IO system Refer to Chapter 4 Developing with LabVIEW FPGA for information about configuring clocks with LabVIEW FPGA The NI 7935R clocking architecture includes the following clocks 10 MHz Reference C...

Page 36: ...on the NI 7935R Figure 3 15 NI 7935R Clocking Diagram Memory Controller PLL 40 MHz 100 MHz 100 MHz 10 MHz Reference Clock Kintex 7 FPGA 200 MHz DRAM Clock 166 MHz MGT Oscillator MGT Ref Clk 156 25 MH...

Page 37: ...uide for your NI 793xR device Adding the NI 793xR to a LabVIEW Project 1 Launch LabVIEW The LabVIEW Getting Started window appears 2 Click Create Project or open an existing project 3 Right click the...

Page 38: ...e You also can drag and drop existing items into the FPGA target in the Project Explorer window Adding NI 793xR Target I O Complete the following steps to add target I O for the NI 793xR and to access...

Page 39: ...ou can use the system configuration API to programmatically set the bitfile that is auto loaded on power up Interactive Front Panel Communication Use interactive front panel communication to communica...

Page 40: ...communication network in LabVIEW FPGA Standard communication methods such as using controls and indicators to pass information between the host and the FPGA may not scale well for large applications U...

Page 41: ...ry also adds support for arbitration between the read and write ports of DRAM Compiling LabVIEW FPGA VIs You may need to purchase and install additional licenses to compile FPGA designs that incorpora...

Page 42: ...ecause the FlexRIO adapter module can generate far more data than the application nodes can process The FPGA to Host FIFO uses Ready for Input signals to communicate to the DRAM whether it is ready to...

Page 43: ...tions in the readiness of the host memory However sizing the FIFO larger consumes block RAM resources on the FPGA and increases the timing pressure on the FIFO NI recommends making the FIFO as large a...

Page 44: ...ar in your VI Complete the following steps to change the application instance for your simulated FPGA VI 1 Navigate to the bottom left corner of the front panel window or block diagram The application...

Page 45: ...opment Process If the sample project code is sufficient for your application you do not have to modify the IP core update the VHDL CLIP wrapper or refresh the CLIP Update VHDL CLIP Wrapper Modify rege...

Page 46: ...itry external to the FPGA Allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface Socketed CLIP Architecture Figure 5 2 shows an overview of th...

Page 47: ...NIFPGA programs Vivado2013_4 3 Run the Xilinx Vivado batch file XilinxVivadoDir bin vivado bat You may receive the following warning when launching Vivado Your XILINX_EDK environment variable is unde...

Page 48: ...urora sample projects for an example of how to use the LabVIEW FPGA AXI4 Lite adapters to connect to DRP within the CLIP Modifying Third Party IP Core Logic If you modify a third party IP core for you...

Page 49: ...ow to generate an EDIF netlist from the IP core 1 Open the example project for your IP core in Vivado 2 Set the appropriate top level source file for which you plan to generate a netlist 3 Run synthes...

Page 50: ...or example to create an edf for clock_module_i enter the following command write_edif cell clock_module_i aurora_64b66b_clock_module edf Note You may have to specify a longer path name depending on th...

Page 51: ...you expose an AXI4 Lite endpoint use Xilinx AXI4 interconnect IP to expose only one AXI4 Lite endpoint to the LabVIEW FPGA diagram Document the frequency of clocks coming from CLIP Consider supportin...

Page 52: ...need to specify the location of the component within the overall VHDL hierarchy In such cases consider prefacing the constraints with the following macros Prefacing allows the constraints to be appli...

Page 53: ...ribing which signals are used which signals are unused and the manner in which the signal is used Signal use can affect which ports are active with your IP and the behavior of cables upon ingestion an...

Page 54: ...LIP using the dialog box or you can click on the Create File icon to create a new CLIP using the CLIP Wizard Note You can modify a CLIP by selecting the preexisting CLIP Declaration Name and clicking...

Page 55: ...lank 12 Click OK Refer to Chapter 3 Hardware Architecture for more information about NI 793xR clocking capabilities Using Existing VHDL IP inside CLIP or IPIN To use existing IP in your project refer...

Page 56: ...rations within a given time limit Maximizing determinism is often a priority when designing real time applications Jitter The time difference between the fastest and slowest executions of the applicat...

Page 57: ...cts like a fixed size queue where the first value you write to the FIFO queue is the first value that you can read from the FIFO queue An RT FIFO ensures deterministic behavior by imposing a size rest...

Page 58: ...ch component s operating range Note All temperatures are reported in degrees Celsius C Note CPU Temp 1 and FPGA Temp are both on die temperature sensors for their respective component CPU Temp 2 and C...

Page 59: ...work Additionally a device status message appears in MAX under the FPGA item that has been shut down If the FPGA communication shuts down power cycle the system and contact NI customer support at ni...

Page 60: ...the same VI LabVIEW on the host computer displays the front panel of the VI while the RT Engine executes the block diagram A user interface thread handles the communication between LabVIEW and the RT...

Page 61: ...g with the front panels of RT target VIs refer to the Interacting with the Front Panels of RT Target VIs topic in the LabVIEW Real Time Module Help Note The Interacting with the Front Panels of RT Tar...

Page 62: ...to the Real Time Module LabVIEW Real Time Module Release and Upgrade Notes The LabVIEW Real Time Module Release and Upgrade Notes contains information to help you install and configure the Real Time M...

Page 63: ...P Signals Port Direction Clock Domain Description MGT_RefClk0_p In pad Differential input clock that you must connect to an IBUFDS_GTE2 input buffer primitive when this input clock is used in your des...

Page 64: ...rom the LabVIEW FPGA VI in the CLIP until aResetS1 is deasserted Port 0 1 _RX_p In pad Dedicated MGT receive signals for Port 0 1 Port 0 1 _RX_n In pad Port 0 1 _TX_p Out pad Dedicated MGT transmit si...

Page 65: ...drain This signal is also called MODDEF1 Port 0 1 _SDA In Out Async Bidirectional serial data signal for the two wire communication interface on the Port 0 1 connector Valid values 0 and Z open drain...

Page 66: ...an over power condition is detected Table A 2 NI 7935R CLIP Signals Port Direction Clock Domain Description MGT_RefClk0_p In pad Differential input clock that you must connect to an IBUFDS_GTE2 input...

Page 67: ...puts from the LabVIEW FPGA VI in the CLIP until aResetS1 is deasserted Port 0 1 _RX_p In pad Dedicated MGT receive signals for Port 0 1 Port 0 1 _RX_n In pad Port 0 1 _TX_p Out pad Dedicated MGT trans...

Page 68: ...This signal is also called MODDEF1 Port 0 1 _SDA In Out Async Bidirectional serial data signal for the two wire communication interface on the Port 0 1 connector Valid values 0 and Z open drain This s...

Page 69: ...the power supply to Port 0 1 This signal is active high sPort 0 1 _ PowerGood In SocketClk40 Indicates that the power supply to the cable for Port 0 1 is enabled This signal may deassert if an over po...

Page 70: ...e NI 793xR includes a replaceable fan assembly For fan troubleshooting information and to order replacement parts refer to ni com support Table B 1 NI 793xR Fan Specifications Manufacturer Sanyo Denki...

Page 71: ...you identify your systems accuracy and reliability requirements and provides warranty sparing and calibration services to help you maintain accuracy and minimize downtime over the life of your system...

Page 72: ...tions Engineers make sure every question submitted online receives an answer Software Support Service Membership The Standard Service Program SSP is a renewable one year subscription included with alm...

Page 73: ...communication mechanism used to read and write DRAM DRAM Dynamic random access memory F FPGA Field programmable gate array NI 793xR modules use Xilinx Kintex 7 FPGAs G GPIO General purpose input outpu...

Page 74: ...Glossary G 2 ni com P PFI Programmable function interface S SCTL Single cycle timed loop SFP Enhanced small form factor pluggable V VHDL VHSIC Hardware Description Language...

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