© National Instruments
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A-5
aResetSl
In
Async
This signal is not required.
This signal is an asynchronous
reset signal from the
LabVIEW FPGA environment.
If you create an input signal to
your CLIP and assign it as
Reset
in the CLIP wizard, that signal is
driven as an asynchronous reset
signal. Reset all CLIP state
machines and logic whenever
this signal is logic high.
This signal is driven high when
you call the LabVIEW FPGA
Reset
invoke method. Call
Run
on the FPGA VI to deassert this
signal.
Do not use CLIP inputs from the
LabVIEW FPGA VI in the CLIP
until
aResetS1
is deasserted.
Port<0..1>_RX_p
In (pad)
—
Dedicated MGT receive signals
for Port <0..1>.
Port<0..1>_RX_n
In (pad)
—
Port<0..1>_TX_p
Out (pad)
—
Dedicated MGT transmit signals
for Port <0..1>.
Port<0..1>_TX_n
Out (pad)
—
Port<0..1>_Tx_Fault
In
Async
When high, indicates a laser
fault. Low indicates normal
operation.
Port<0..1>_LOS
In
Async
When high, this input indicates
that the received optical power is
below the worst-case receiver
sensitivity. Low indicates
normal operation.
Port<0..1>_ABS
In
Async
When high, this input indicates
that a module is plugged into the
SFP+ socket. Low indicates that
a module has been detected.
Table A-2.
NI-7935R CLIP Signals (Continued)
Port
Direction
Clock Domain
Description
