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5-11
7.
Instantiate the CLIP in the MGT Socket. When you add a new target to the project,
LabVIEW automatically creates a compatible MGT Socket in the project. Right-click the
socket and select
Properties
, then select
General
under
Category
.
8.
Select a declaration from the drop-down menu under
Socketed Component Level IP
Declaration
.
9.
Click
OK
. The user-defined signals in your CLIP appear under the socket item in the
Project Explorer
window.
10. Right-click the MGT Socket and select
Clocking Selections
under
Category
to configure
the Clocking and IO Configuration properties for your device.
Note
Clocking and routing information is compile-time static and cannot be
reconfigured at runtime.
Note
The NI-793xR devices support empty sockets.
11. Select the clock that your CLIP requires and explicitly assign it a connection. You must add
the clock to your LabVIEW project in order to select it from the
Connections
window. If
your CLIP does not require any clocks, leave this page blank.
12. Click
OK
.
Refer to Chapter 3,
, for more information about NI-793xR clocking
capabilities.
Using Existing VHDL IP inside CLIP or IPIN
To use existing IP in your project, refer to the
Importing External IP Into LabVIEW FPGA
white
paper at
ni.com
.
CLIP does not support custom user libraries in the VHDL. If your VHDL uses custom user
libraries, use one of the following workarounds:
•
Create a netlist from the VHDL and integrate the netlist using CLIP.
•
Reference the default reference library instead of a custom user library.
Refer to the
Creating or Acquiring IP (FPGA Module)
topic in the
LabVIEW FPGA Module
Help
for more information about using existing VHDL IP inside CLIP or IPIN.
Improving Performance in Larger Designs through
Enable Chain Removal
By default, LabVIEW adds code to the FPGA code to enforce data flow. This code addition is
referred to as the enable chain. In larger applications, the enable chain can create routing
congestion and limit performance. You can remove the enable chain under certain
circumstances. Refer to
Improving Timing Performance in Large Designs (FPGA Module)
in the
LabVIEW FPGA Module Help
for more information about how to remove enable chains and
when to do so.
