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Chapter 5
Programming the High-Speed Serial Ports
Generating an IP Core from the Xilinx Vivado IP Catalog
You may need to purchase and install additional licenses to generate some protocol IP core from
Xilinx or third-party IP vendors. Refer to
UG 973: Vivado Design Suite: Release Notes,
Installation, and Licensing
at
xilinx.com
for information about managing licenses.
Complete the following steps to create a Xilinx Vivado project:
1.
Refer to the
section of this manual for information about licensing
before creating a Xilinx Vivado project.
2.
Launch the Xilinx Vivado IP catalog.
a.
Select
Manage IP
on the Vivado start screen.
b.
Locate the appropriate IP core to launch the configuration dialog. For example, the
Aurora 64B66B IP core is located in
Communication and Networking»Serial
Interfaces»Aurora 64B66B
.
3.
Select the IP core settings. NI recommends that you select AXI4-Stream for high-speed
data streams when possible.
Note
NI does not recommend selecting AXI4-Lite for DRP accesses in the Xilinx
IP cores because compatibility with LabVIEW FPGA AXI4-Lite adapters cannot be
guaranteed. Refer to the Aurora sample projects for an example of how to use the
LabVIEW FPGA AXI4-Lite adapters to connect to DRP within the CLIP.
Modifying Third-Party IP Core Logic
If you modify a third-party IP core for your high-speed serial protocol, consult the
Xilinx
Product Guide
for the IP you are using before attempting to make any modifications.
Adhere to the following guidelines when modifying third-party IP core logic:
•
Ensure all clocks are connected.
•
Ensure AXI4-Lite management signals are connected correctly to the Xilinx DRP signals
on the GTXE2_CHANNEL and GTXE2_COMMON primitives.
•
Select
Include Shared Logic in example design
in the IP wizard to access various
resources outside of the IP core logic, such as MGT_RefClk input buffers and QPLL
wrappers.
The following examples explain the differences in how the IBUFDS_GTE2 resource is exposed
with and without the
Include Shared Logic in example design
option.
•
Option 1: Include the IBUFDS_GTE2 input buffer primitive inside the core by selecting
Include Shared Logic in core
in the IP wizard. The image on the left in Figure 5-4 shows
this option.
•
Option 2: Instantiate a single IBUFDS_GTE2 input buffer in your top level CLIP VHDL,
connect its output signal to both cores, and select
Include Shared Logic in example design
in the IP wizard. The image on the right in Figure 5-4 shows this option.
