OPERATING INSTRUCTIONS
M68HC11EVB/D
4-9
9
ASM
Assembler/Disassembler
When a new source line is assembled, the assembler overwrites what was previously in memory. If
no new source line is submitted, or if there is an error in the source line, then the contents of
memory remain unchanged. Four instruction pairs have the same opcode, so disassembly will
display the following mnemonics:
•
Arithmetic Shift Left (ASL)/Logical Shift Left (LSL) displays as ASL
•
Arithmetic Shift Left Double (ASLD)/Logical Shift Left Double (LSLD) displays as
LSLD
•
Branch if Carry Clear (BCC)/Branch if Higher or Same (BHS) displays as BCC
•
Branch if Carry Set (BCS)/Branch if Lower (BLO) displays as BCS
If the assembler tries to assemble at an address that is not in RAM or EEPROM, an invalid
address message "rom-xxxx" is displayed on the terminal CRT (xxxx = invalid address).
Assembler/disassembler subcommands are as follows. If the assembler detects an error in the new
source line, the assembler will output an error message and then reopen the same address
location.
/
Assemble the current line and then disassemble the same address location.
^
Assemble the current line and then disassemble the previous sequential
address location.
<CR>
Assemble the current line and then disassemble the next opcode address.
(CTRL)J
Assemble the current line. If there isn't a new line to assemble, then
disassemble the next sequential address location. Otherwise, disassemble
the next opcode address.
(CTRL)A
Exit the assembler mode of operation.
Summary of Contents for M68HC11EVB
Page 9: ...CONTENTS x M68HC11EVB D ...
Page 35: ...MONITOR PROGRAM 3 8 M68HC11EVB D ...
Page 81: ...OPERATING INSTRUCTIONS 4 46 M68HC11EVB D ...
Page 97: ...SUPPORT INFORMATION 6 12 M68HC11EVB D Figure 6 3 EVB Schematic Diagram Sheet 2 of 2 ...
Page 103: ...APPLICATIONS B 2 M68HC11EVB D Figure B 1 Single Chip Mode Configuration ...