23
ECP5 and ECP5-5G Hi
g
h-Speed I/O Interface
Figure 23 shows that max value after which the data cannot transition is tDIA_GDDRX1/X2. The min value before
which the data cannot transition is – tDIB_GDDRX1/X2. Negative sign is used for the min value is because in this
particular case the min condition occurs before the clock edge.
The clock to out time in the software can be specified as –
CLOCK_TO_OUT PORT “dataout” MAX <tDIA_GDDRX1/X2> MIN <-tDIB_GDDRX1/X2> CLKPORT “clk” CLK-
OUT PORT “clk”;
where:
Data = Data Output Port
Clock = Forwarded Clock Output Port
clk = Input Clock Port
Both tDIA_GDDRX1/X2 and tDIB_GDDRX1/X2 numbers are available in the External Switching Characteristics
section of DS1044,
ECP5 and ECP5-5G Family Data Sheet
for maximum speed.
Preference Example:
For GDDRX2_TX.Aligned case running at 400 MHz, tDIA_GDDRX2= tDIB_GDDRX2=0.16ns. The preference
would be -
CLOCK_TO_OUT PORT "dataout" MAX 0.16 ns MIN -0.16ns CLKPORT "clk" CLKOUT PORT "clkout”;
Note: Please check DS1044,
ECP5 and ECP5-5G Family Data Sheet
for the latest tDIA_GDDX1/X2 and
tDIB_GDDRX1/X2 numbers
ECP5 and ECP5-5G Memory Interfaces
All of the DDR SDRAM interface transfers data at both the rising and falling edges of the clock. The I/O DDR regis-
ters in the ECP5 and ECP5-5G device can be used to support DDR2, DDR3, DDR3L, LPDDR2 and LPDDR3
memory interfaces.
These memory interfaces rely on the use of a data strobe signal, called DQS, for high-speed operation. The DQS
strobe is a differential signal except for DDR2 you can choose between single-ended or differential DQS strobe.
Figure 24 shows typical DDR memory signals. DDR2, DDR3 and DDR3L memory interfaces are typically imple-
mented with either four or eight DQ data bits per DQS. So, a 16-bit DDR memory interface will use two or four DQS
signals, and each DQS is associated with four or eight DQ bits, respectively. Both the DQ and DQS are bi-direc-
tional ports and are used to read and write to the memory. LPDDR2 and LPDDR3 memory are the same but will
only support 8 DQ data bits per DQS strobe.
When reading data from the external memory device, data coming into the FPGA controller is edge-aligned with
respect to the DQS signal. This DQS strobe signal needs to be phase shifted 90° before the FPGA logic can sam-
ple the read data. When writing to a DDR memory, the memory controller (FPGA) must shift the DQS by 90° to
center-align with the data signals (DQ). A clock signal is also provided to the memory. This clock is provided as dif-
ferential clock (CK and CK#) to minimize duty cycle variations. The memory also uses these clock signals to gener-
ate the DQS signal during a read via a DLL inside the memory. The figures below show DQ and DQS timing
relationships for read and write cycles.
During read, the DQS signal is low for some duration after it comes out of tristate. This state is called Preamble.
The state when the DQS is low before it goes into tristate is the Postamble state. This is the state after the last valid
data transition.