22
ECP5 and ECP5-5G Hi
g
h-Speed I/O Interface
The DS1044,
ECP5 and ECP5-5G Family Data Sheet
specifies the t
DVB_GDDRX1/X2
and t
DVA_GDDRX1/X2
values at
maximum speed. But we do not have the tU value hence min t
CO
can be calculated using the following equation.
t
CO
Min = - (t
VB_GDDRX1/X2
+ t
U
)
½ T = t
DVA_GDDRX1/X2
+ t
VB_GDDRX1/X2
+ t
U
- (t
VB_GDDRX1/X2
+ t
U
) = 1/2T - t
DVA_GDDRX1/X2
t
CO
Min = 1/2T - t
DVA_GDDRX1/X2
The clock to out time in the software can be specified as –
CLOCK_TO_OUT PORT “dataout” MAX <-t
DVB_GDDRX1/X2
> MIN <t
DVA_GDDRX1/X2
-1/2 Clock Period> CLKPORT
“clk” CLKOUT PORT “clkout”;
where:
Data = Data Output Port
Clock = Forwarded Clock Output Port
clk = Input Clock Port
The values for t
DVBCKGDDR
and t
DVACKGDDR
can be picked up from the External Switching Characteristics section
of DS1044,
ECP5 and ECP5-5G Family Data Sheet
for the MAX speed.
Preference Example:
For GDDRX1_TX.SCLK.Centered interface running at 250
MHz
, tDVB_GDDRX1 = tDVA_GDDRX1 = 0.67ns, the
preference would be -
CLOCK_TO_OUT PORT "dataout" MAX -0.670000 ns MIN -1.330000 ns CLKPORT "clk" CLKOUT PORT "clkout”;
Note: Please check DS1044,
ECP5 and ECP5-5G Family Data Sheet
for the latest tDVAGDDR and tDVBGDDR
numbers.
Transmit Aligned Interfaces
In this case the clock and data are aligned when leaving the device. Figure 23 below shows the timing diagram for
this interface.
tDIAGDDR = Data valid after clock.
tDIBGDDR = Data valid before clock.
Figure 23. Transmit Aligned Interface Timing
