31
ECP5 and ECP5-5G Hi
g
h-Speed I/O Interface
Figure 30. READ signal Training Process
Note that the DYNDELAY[7:0] signal, margin control signals (WR/RDMOVE, WR/RDLOADN) and DDRDLL update
signal (UDDCNTLN) also have the same PAUSE requirement.
Dynamic Mar
g
in Control on DQSBUF
The ECP5 and ECP5-5G family includes dynamic margin control signals in the DQSBUF module will allow user to
dynamically adjust the read or write side DQS delays generated in the DDRDLL.
Once the margin control mode is enabled by de-asserting WRLOADN (=1) or RDLOADN (=1), the DQSBUF’s
phase shift control to make a center aligned interface is no longer controlled by the DDRDLL component. It
becomes a user’s responsibility to complete the margin control training to maximize the valid window and then con-
tinuously monitor the DDRDLL delay code (DCNTL7~DCNTL0) and controls the DQSBUF delays accordingly
using the WR/RDMOVE and WR/RDDIRECTION signals to compensate the PVT variations.
Read Data Clock Domain Transfer Usin
g
Input FIFO
Each IDDR module in the ECP5 and ECP5-5G device has a dedicated input FIFO to provide a safe clock domain
transfer from the DQS domain to the ECLK or SCLK domain. The input FIFO is 8-level deep with 3-bit write and
read pointers. It transfers the read data from the non-continuous DQS domain to the continuous ECLK. The FIFO is
written by the DQS strobe and read back by ECLK which has the identical frequency rate as DQS.
The input FIFO also performs the read leveling function. When each DQS strobe signal and its associated DQ data
signals arrive at slightly different time with others to the FPGA, the input FIFO allows the skewed read data to be
captured and transferred properly.
Each DQS group has one FIFO control in the DQSBUF block. It distributes the FIFO read/write pointers, WRPNTR
[2:0] and RDPNTR [2:0], to each memory IDDR module in the same DQS group. Safe domain crossing between
ECLK and SCLK is guaranteed by the ECP5 and ECP5-5G device hardware design.
DDR Input and Output Re
g
isters (IDDR/ODDR)
ECP5 and ECP5-5G devices provide dedicated input DDR (IDDR) and output DDR (ODDR) functions supporting
4:1(X2) gearing modes that are used to implement the DDR memory functions. These automatically handle the
transfer of data from ECLK domain to the SCLK (FPGA clock) domain.
ECLK
CK
DQSI
READ1
READ 0
BURST_DET
5.5T
DQSI
READ1
READ 0
BURST_DET
7.5T
DQS round trip
delay is ~+2T
Simulation timing without
DQS round trip
Actual board timing with
DQS round trip
3-bit code for adjusting the internal READ pulse 1/4T per step, can be changed only during PAUSE assertion
READCLKSEL 2/ 1/ 0
Indicates that the internal READ pulse is properly aligned
t0
t1
t0
t0
t 0
t 1
t0
t1
Internal READ pulse with
allocated time slot
Internal READ pulse with
allocated time slot
SCLK
t1
t1
t0
t0
t1
t0
t1
t0
t0
t1
