manualshive.com logo in svg

Lattice Semiconductor ECP5 Versa, Technical Notes, Page: 76 / 78

Share
Download
Lattice Semiconductor ECP5 Versa Technical Notes Download Page 76

76

ECP5 and ECP5-5G Hi

g

h-Speed I/O Interface

BW_ALIGN

This module is used to perform 7:1 video RX bit and word alignment. This module is optional and can be enabled in 
Clarity Designer.

Figure 71. BW_ALIGN Ports

Table 43. BW_ALIGN Port Description

With Bit Alignment, the goal is to place edge clock (under PLL dynamic phase shift control) to the center of valid 
window for the clock word and data words. The PLL phase rotation goes through all 16 phases. The PLL’s high 
speed output is used to sample RX input clock. Transitions are detected on 2nd IDDR71 output which inputs the 
RX Clock and phases close to transition are identified. The IP will choose the phase most away from transition as 
the final phase to use. 

The low speed clock has two transitions per 7-bit word. It is not the worst case in terms of inter-symbol interference. 
On the other hand, we do have 8 possible sample points per bit period. Minimum eye-opening of 3/8 UI is needed 
to achieve lock. Jitter tolerance is around 0.25UI, about 300ps at 756Mb/sec.

After bit alignment is achieved, word alignment is needed so video data (in 7-bit words) can be processed in core. 
The IP uses the “ALIGNWD” function of the IDDRX71 primitive for word alignment. Each pulse on ALIGNWD 
rotates the 7-bit bus by 2 bits. In maximum 7 ALIGNWD operations, the word will loop through all 7 possibilities. 
The goal is to get “7’b1100011” (7’h63) in the clock word. The clock word is the clock (4 bit 1 and 3’b 0) converted 
to parallel data, exactly as the video data traffic. For the 7:1 video, the RX input Clock serves as:

• Frequency reference to generate high speed.

• Phase reference as source synchronized RX, since the clock is edge aligned with the data bits.

• Word alignment reference.

Port

In/Out

Descriptions

RX_SCLK

IN

Divided RX clock from the 7:1 RX interface, produced by CLKDIV.

RST

IN

Active high reset to this circuit. When RST=1, 
All outputs=0.

PLL_LOCK

IN

Connect to PLL’s LOCK output. Start the alignment procedures after PLL lock 
goes high.

UPDATE

IN

Start the procedure, or re-start if need to optimize again.

RXCLK_WORD<6:0>

IN

Parallel data output from the 2nd IDDRX71 attached to RX CLK Input.

PHASESTEP

OUT

Rotate phase for PLL

PHASEDIR

OUT

Phase rotation direction for PLL, fixed to forward (0) for this design.

ALIGNWORD

OUT

Connect to IDDRX71.ALIGNWORD, for word rotation.

WINDOW_SIZE

OUT

Final valid window size.

BIT_LOCK

OUT

Status output, bit lock has been achieved.

WORD_LOCK

OUT

Status output, word lock has been achieved.

READY

OUT

Indicate that alignment procedure is finished and RX circuit is ready to operate

RX_ SCLK

RXCLK_ WORD <6 :0 >

UPDATE

PLL_ LOCK

RST

PHASESTEP

PHASEDIR

ALIGNWORD

WINDOW_ SIZE

BIT _ LOCK

WORD_ LOCK

READY

BW_ALIGN

Summary of Contents for ECP5 Versa

Page 1: ...discusses how to utilize the capabilities of the ECP5 and ECP5 5G devices to implement high speed generic DDR interface and the DDR memory interfaces Refer to the Implementing DDR Memory Interfaces se...

Page 2: ...these edge clocks can be used to implement a high speed interface There is an Edge Clock Bridge ECLKBRIDGECS that will allow users to build large interfaces by bridg ing the edge clocks from one bank...

Page 3: ...when interfacing to DDR memories It generates the delay on the DQS pin of the DQS lane to provide a 90o phase shift on DQS to clock the DDR data at the center The delay is set by a delay code generat...

Page 4: ...t Similar to input interfaces the 2X gearing is used for data rate higher than 400Mbps which would require higher than 200 MHz system clock Here the ODDR element receives 4 bit wide data from the FPGA...

Page 5: ...Aligned GDDRX1_RX SCLK Aligned DDR 1x Input using SCLK Data is edge to edge with incoming clock DLLDEL will be used to shift the incoming clock Receive DDRX1 Centered GDDRX1_RX SCLK Centered DDR x1 I...

Page 6: ...eric 1X gearing Receive interface using SCLK The clock is coming in centered to the Data This inter face must be used for speeds below 200 MHz This DDR interface uses the following modules IDDRX1F ele...

Page 7: ...YG and DELAYF element to indicate the interface type so that the cor rect delay value can be set in the delay element Dynamic Margin adjustment in the DDRDLLA module can be optionally used to adjust t...

Page 8: ...y set The type of delay required can be selected through Clarity Designer DEL_MODE attribute is used with DELAYG and DELAYF element to indicate the interface type so that the cor rect delay value can...

Page 9: ...t the incoming clock routed to the Edge clock ECLK clock tree through the ECLKSYNCB module CLKDIVF module is used to divide the incoming clock by 2 Static data delay element DELAYG to delay the incomi...

Page 10: ...The Receiver Synchronization RX_SYNC soft IP is required for the aligned interfaces to prevent stability issues that may occur due to this loop at startup The soft IP will prevent any updates to the D...

Page 11: ...en by a soft IP When in high speed mode The OHSOLS1 of the element is active The OHSOLS1 of the data IMIPI element is connected to the Data input GDDRX2_RX ECLK Centered Interface The OHSOLS1 of the c...

Page 12: ...the Edge clock ECLK clock tree through the ECLKSYNCB module CLKDIVF module is used to divide the ECLK by 3 5 and is routed to the primary clock tree used as the SCLK input A second IDDRX71B element i...

Page 13: ...ace uses the following modules ODDRX1F element is used to generate the data output The primary clock SCLK is used as the clock for both data and clock generation Optionally the user can choose to use...

Page 14: ...rate the clock output is delayed 90 to center to data at the output Both these clocks are routed on primary clock tree Optionally the user can choose to use the DELAYG or DELAYF element to delay the o...

Page 15: ...tionally the user can choose to use the DELAYG or DELAYF element to delay the data output The output data can be optionally tristated using either a Tristate input going through an I O register Figure...

Page 16: ...ed to the SCLK net The user must set the timing preferences as per section Timing Analysis Requirement GDDRX71_TX ECLK This interface is used to implement transmit side of the 7 1 LVDS interface DDR u...

Page 17: ...etails Receive Interface Guidelines Differential DDR interface can be implemented on the Left and Right sides of the device There are 4 different edge clocks available per side two per bank Each of th...

Page 18: ...aring will use the primary clock resource You can use as many interfaces as the num ber of primary clocks supported in the device Clocking Guidelines for Generic DDR Interface The edge clock and prima...

Page 19: ...or DLL DDR Input Setup and Hold Time Constraints All of the Receive RX interfaces both x1 and x2 can be constrained with setup and hold preference Receive Centered Interface Figure 19 below shows the...

Page 20: ...CLKPORT clk Note Negative number is used for SETUP time as the data occurs after the clock edge in this case The External Switching Characteristics section of DS1044 ECP5 and ECP5 5G Family Data Sheet...

Page 21: ...ax Timing Analysis Transmit Centered Interfaces In this case the transmit clock is expected to be centered to the data when leaving the device Figure 22 shows the timing for a centered transmit interf...

Page 22: ...k Output Port clk Input Clock Port The values for tDVBCKGDDR and tDVACKGDDR can be picked up from the External Switching Characteristics section of DS1044 ECP5 and ECP5 5G Family Data Sheet for the MA...

Page 23: ...e signal called DQS for high speed operation The DQS strobe is a differential signal except for DDR2 you can choose between single ended or differential DQS strobe Figure 24 shows typical DDR memory s...

Page 24: ...eveling may be supported if user emulates the fly by rout ing using board traces You can see more information in the DDR pin placement and layout guidelines section of this document One major differen...

Page 25: ...l LPDDR2 LPDDR3 Memory Interface Figure 26 DQ DQS During Read Figure 27 DQ DQS During Write DQS at PIN DQ at PIN DQS at IDDR DQ at IDDR 90 degree phase shift between DQS pin to IDDR Preamble Postamble...

Page 26: ...multiplexed into a single outgoing DDR data stream Generate ADDR CMD signal edge aligned to CK falling edge to maximize the tIS and tIH timing parameters Differential CK signals CK and CK need to be g...

Page 27: ...these DDR interface needs ECP5 and ECP5 5G devices support DQS signals on the left and right sides of the device Each DQS signal spans across 12 to 16 I Os Any 10 for DDR2 or 11 for DDR2 DDR3 LPDDR2...

Page 28: ...de DDRDEL from the on chip DDRDLL The code generated by DDRDLL is connected to the DQSBUF circuit to perform 90 read phase shift and 90 write phase shift DDRDLL requires the frequency reference from P...

Page 29: ...e READ1 0 signal must stay asserted as long as the number of SCLK cycles that is equal to one fourth of the total burst length as listed in the Table 4 Table 4 READ Training Signals and Initial Read A...

Page 30: ...AD pulse needs to be moved to the next timing window Step 3 To shift the READ pulse timing window READ1 0 can be moved to the next cycle If a READ bit is asserted in the next cycle while the other REA...

Page 31: ...e continuous ECLK The FIFO is written by the DQS strobe and read back by ECLK which has the identical frequency rate as DQS The input FIFO also performs the read leveling function When each DQS strobe...

Page 32: ...e DQSBUFM module to the DQS clock tree The DQSBUFM receives the delay code from DDRDLLA and generates the delayed DQS signal to IDDRX2DQA DQSR90 D Q0 Q1 RST SCLK RDPNTR 2 0 WRPNTR 2 0 IDDRX2DQA DQSR90...

Page 33: ...n without interrupting interface operation When a DDR memory interface IP is gen erated from Clarity Designer the MEM_SYNC soft IP block is also generated and included The Pause_sync output of the MEM...

Page 34: ...ed inside the ODDRX2 module before data is transferred to the DQSW270 and DQSW clocks The ECLK is generated by the EHXPLLL module and the SCLK is generated by the CLKDIVF module both shown in the Read...

Page 35: ...3 ODDRX2DQA module to generate the CA 9 0 outputs ODDRX2DQSB with D0 and D1 tied together and D2 and D3 tied together to generate CSN CKE signals ODDRX2DQSB with inputs tied to 0 and 1 is used to gene...

Page 36: ...W270 D2 D3 SCLK ca n _in 0 ECLK DQSW Q PAUSE Pause_CA From Input side DDRDLLA CA 9 0 0 0 ca n _in 1 ca n _in 2 ca n _in 3 0 Pause output of MEM_SYNC Eclk from ECLKSYNCB as shown in the Input interface...

Page 37: ...YNDELAY 7 0 PAUSE SCLK DQSW270 ECLK DQSW DQSR 90 WRPNTR 2 0 RDPNTR 2 0 DDR_reset Sclk from CLKDIVF as shown in the Input interface Eclk from ECLKSYNCB as shown in the Input interface D0 D1 SCLK RST Q...

Page 38: ...side where another DDR memory interface is running at a differ ent frequency another available DDRDLLA for the side must be instantiated and used for the new interface The reference clock input to the...

Page 39: ...Locate a 100 ohm resistor between the positive and negative clock signal OR Connect one end of an Rtt resistor to the positive pin and one end of another Rtt to the negative pin of a CK pair then conn...

Page 40: ...ial SSTL type SSTL15D in DDR3 SSTL18D in DDR2 SSTL135D in DDR3L and HSUL12D in LPDDR2 LPDDR3 is selected Do not assign any signal to a DQS pad if used as differential strobe The software automatically...

Page 41: ...or ground power source on the PCB Your design needs to drive the pseudo power I O pads according to the external connection i e you assign them as OUTPUT and let your design drive 1 for pseudo VCCIO...

Page 42: ...hat includes all the DDR modules configured Planner Used to Plan the Placement of the various DDR Interfaces Figure 38 Clarity Design Main Window Note It is recommend that all the DDR modules required...

Page 43: ...Clarity Designer Enter the name of the module Figure 39 shows the type of interface selected as SDR and module name entered This module can then be configured by clicking the Customize button Figure...

Page 44: ...ce 1 256 16 Clock Frequency for this Interface Interface Speed 1 200 200 Bandwidth Calculated This is the calculated from the Clock frequency entered Calculated calculated Interface Interface selected...

Page 45: ...ith the best interface selection The user can also if needed override the selection made for the interface in the Configuration Tab and customize the interface based on the design requirement FDEL for...

Page 46: ...ulated with the selections Figure 43 shows the Configuration Tab for the selection made in Pre Configuration Tab GUI Option Range Interface Type Transmit Receive Receive MIPI I O Standard for this Int...

Page 47: ...ers GUI Option Description Values Default Value Interface selection based on pre configuration Indicates interface is selected based on selection made in the Pre configuration tab Disabling this check...

Page 48: ...nterfaces available for a given configuration Data Path Delay Data input can be optionally delayed using the DELAY block Default Value is selected based on Interface Type If Interface Type Receive Sta...

Page 49: ...ays the achieved PLL output clock frequency Actual PLL output Fre quency achieved based on interface requirement CLKI Input Buffer Type The I O Standard for the PLL Ref erence Clock List of Legal Inpu...

Page 50: ...rface Figure 44 GDDR_7 1 Option Selected in the Catalog Tab of Clarity Designer Clicking Customize displays the Configuration Tab where the 7 1 LVDS interface can be configured Figure 45 shows the Con...

Page 51: ...ce select DDR_MEM option under Architecture Modules IO in the Catalog Tab of Clarity Designer Enter the name of the module Figure 46 shows the type of interface selected as GDDR_MEM and module name en...

Page 52: ...52 ECP5 and ECP5 5G High Speed I O Interface Figure 46 DDR_MEM Option Selected in the Catalog Tab of Clarity Designer Figure 47 shows the Configuration Tab for the DDR_MEM interface...

Page 53: ...or DDR pins DDR2 SSTL18_I STL18_II DDR3 SSTL15_I SSTL15_II DDR3L SSTL135_I SSTL135_II LPDDR2 HSUL12 LPDDR3 HSUL12 DDR2 SSTL18_I DDR3 SSTL15_I DDR3L SSTL135_I LPDDR2 HSUL2 LPDDR3 HSUL12 DDR Memory Freq...

Page 54: ...DR2 DQS IO buffer type selection Single ended Differential Single ended Clock Address Com mand Clock address command pins added with this option checked ENABLED DISABLED DISABLED Data Mask Data mask p...

Page 55: ...Command Parameters GUI Option Range Default Value Number of Clocks DDR2 1 2 4 DDR3 1 2 4 DDR3L 1 2 4 LPDDR2 1 LPDDR3 1 DDR3 1 DDR2 1 DDR3L 1 LPDDR2 1 LPDDR3 1 Address Width DDR2 13 16 DDR3 13 16 DDR3...

Page 56: ...Table 13 shows the available values in this tab Number of Chip Selects DDR2 1 2 4 DDR3 1 2 4 DDR3L 1 2 4 LPDDR2 1 LPDDR3 1 DDR2 1 DDR3 1 DDR3L 1 LPDDR2 1 LPDDR3 1 Number of Clock Enables Number of Chi...

Page 57: ...he selected location The planner takes into account all the clocking placement requirements any architecture limitations for each type DDR interface If any of the placement rules are violated the plan...

Page 58: ...58 ECP5 and ECP5 5G High Speed I O Interface Figure 50 DDR Modules Paced Using Clarity Design Planner DDRDLL PLL ECLK tree CLKDIV DQS Group IO Logic...

Page 59: ...alue for Zero Hold time delay based on Interface Type Fixed Delay values entered by the user The data input to this block can also be dynamically updated using counter up and down controls You can opt...

Page 60: ...sing this module Figure 52 DELAYG Primitive Table 16 DELAYG Port List Port I O Description A I Data input from pin or output register block LOADN I 0 on LOADN will reset to default delay setting MOVE...

Page 61: ...elements to delay the DQS input or in the DLLDEL module to delay the input clock DDRDLL by default will generate 90degree phase shift DDRDLLA Figure 53 DDRDLLA Primitive Attribute Description Values1...

Page 62: ...ZE I Releases the DDRDLL input clock DDRDEL O The delay codes from the DDRDLL to be used in DQSBUF or DLLDEL LOCK O Lock output to indicate the DDRDLL has valid delay output DCNTL 7 0 O The delay code...

Page 63: ...re the primitives used to implement various Generic DDR Input and Output data IDDRX1F This primitive is used to receive Generic DDR with 1X gearing Figure 55 IDDDRX1F Primitive Table 22 IDDRX1F Port L...

Page 64: ...D I DDR data input ECLK I Fast edge clock SCLK I Primary clock input divide by 2 of ECLK RST I Reset to DDR registers ALIGNWD I This signal is used for word alignment It will shift the word by one bit...

Page 65: ...Primitive Port I O Description D0 D1 I Parallel data input to ODDR D0 is sent out first then D1 SCLK I SCLK input RST I Reset input Q O DDR data output on both edges of SCLK Port I O Description D0 D...

Page 66: ...flected in the delay DQS signal A soft IP is required to detect the code changes from the DDRDLL and update the MOVE pulse input to the DQSBUF so that the DDRDLL code changes can be tracked If margin...

Page 67: ...RECTION I Indicates delay direction 1 decreases the delay count 0 increases the delay count Used to change delay on the read side DQS RDCFLAG O Indicates the delay counter has reached max value for th...

Page 68: ...BUF DQS_LI_DEL_ADJ Sign bit for READ delay adjustment DDR input PLUS MINUS PLUS All DQS_LI_DEL_VA Value of delay for input DDR 0 to 255 PLUS 1 to 256 MINUS Note1 All DQS_LO_DEL_ADJ Sign bit for WRITE...

Page 69: ...DQSR90 I DQS clock Input ECLK I Fast edge clock SCLK I Primary clock input divide by 2 of ECLK RDPNTR 2 0 I Read pointer from the DQSBUF module used to transfer data to ECLK WRPNTR 2 0 I Write pointe...

Page 70: ...DR Primitives for DQS Output Following are the primitives used to implement the DQS outputs to the DDR memory ODDRX2DQSB This primitive is used to generate DQS clock output for DDR2 and DDR3 memory Fi...

Page 71: ...tristate control for DQS output Figure 66 TSHX2DQSA Primitive Port I O Description D0 D1 D2 D3 I Data input to the ODDR D0 is output first D3 last ECLK I ECLK input SCLK I SCLK input DQSW I DQSW inclu...

Page 72: ...y with x2 gearing and write leveling Figure 67 OSHX2A Primitive Table 37 OSHX2A Port List Port I O Description T0 T1 I Tristate input T0 is output first then T1 ECLK I ECLK input 2x speed of SCLK SCLK...

Page 73: ...r Aligned Interfaces Yes GDDR_SYNC Needed to tolerate large skew between stop and reset input Yes MEM_SYNC Needed to avoid issues on DDR memory bus and update code in operation without interrupting in...

Page 74: ...he RX_CLK or divided version It can be other low speed continuously running clock For example oscillator clock RST IN Active high reset to this sync circuit When RST 1 STOP 0 DDR_RESET 1 READY 0 START...

Page 75: ...RESET OUT Reset to DDRDLL DDR_RESET OUT Reset to all IDDRX components and CLKDIV READY OUT Indicate that startup is finished and RX circuit is ready to operate Port In Out Descriptions START_CLK IN St...

Page 76: ...es the 7 bit bus by 2 bits In maximum 7 ALIGNWD operations the word will loop through all 7 possibilities The goal is to get 7 b1100011 7 h63 in the clock word The clock word is the clock 4 bit 1 and...

Page 77: ...LK IN Clock used to drive digital filter Min freq 100 MHz Recommendation is to use internal oscillator at 133 MHz LS IN Low speed signal from MIPI PHY RST IN Active high reset When RST 1 LSOUT 0 LS_OU...

Page 78: ...2_RX ECLK Centered Interface Dynamic Data delay Figure 10 GDDRX2_RX ECLK Aligned Interface Static Delay Figure 11 GDDRX2_RX ECLK Aligned Interface Dynamic Data Clock Delay Figure 12 GDDRX2_RX MIPI Fig...

Reviews:

No comments