64
ECP5 and ECP5-5G Hi
g
h-Speed I/O Interface
Table 23. IDDRX2F Port List
IDDR71B
This primitive is used for 7:1 LVDS input side implementation.
Figure 57. IDDR71B
Table 24. IDDR71B Port List
Output DDR Primitives
The following are the primitives used to implement various Generic DDR output configurations.
ODDRX1F
This primitive is used to transmit Generic DDR with 1X gearing.
Figure 58. ODDRX1F
Port
I/O
Description
D
I
DDR data input
ECLK
I
Fast edge clock
SCLK
I
Primary clock input (divide-by-2 of ECLK)
RST
I
Reset to DDR registers
ALIGNWD
I
This signal is used for word alignment. It will shift the word by one bit.
Q0, Q2
O
Data at positive edge of input ECLK
Q1, Q3
O
Data at negative edge of input ECLK
Port
I/O
Description
D
I
DDR data input
ECLK
I
Edge clock
SCLK
I
Primary clock (divide-by-3.5 of ECLK)
RST
I
Reset to DDR registers
ALIGNWD
I
This signal is used for word alignment. It will shift the word by one bit.
Q0 to Q6
O
7 bits of output data.
SCLK
Q0
D
Q1
RST
ALIGNWD
ECLK
Q2
Q3
Q4
Q5
Q6
IDDR71B
D0
D1
SCLK
RST
Q
ODDRX1F