Lattice Semiconductor ECP5 Versa, Technical Notes

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ECP5 and ECP5-5G Hi g h-Speed I/O Interface
Table 2 below shows the different DDR memory configurations and features supported by ECP5 and ECP5-5G
device.
Table 2. DDR Memory Configurations Support
DDR Memory Interface Requirements
As described in the overview section, all the DDR memory interfaces rely on the use of a data strobe signal, called
DQS, for high-speed operation. When reading data from the external memory device, data coming into the ECP5
and ECP5-5G device is edge-aligned with respect to the DQS signal. Therefore, the ECP5 and ECP5-5G device
needs to shift the incoming DQS (90° phase shift) before using it to sample the read data.
To implement the write portion of a DDR memory interface, parallel single data rate data must be multiplexed
depending on the IDDR and ODDR register gearing mode together with data transitioning on both edges of the
clock. In addition, during a write cycle, the ECP5 and ECP5-5G devices generate a DQS signal that is center
aligned with the DQ, the data signal. This is accomplished by ensuring a DQS strobe is 90° shifted relative to the
DQ data. The ECP5 and ECP5-5G devices provide the solutions to achieve the following design challenges to
implement DDR memory write functions:
• DQ/DM needs to be center-aligned to DQS.
• DQS needs to be edge-aligned to CK. In DDR3 interfaces where fly-by routing is used, write leveling should be
used to compensate for skews between CK and DQS.
• The DDR output data must be multiplexed into a single outgoing DDR data stream.
• Generate ADDR/CMD signal edge-aligned to CK falling edge to maximize the tIS and tIH timing parameters.
• Differential CK signals (CK and CK#) need to be generated.
• The controller must meet the DDR interface specification for the tDSS and tDSH parameters, defined as DQS
falling edge setup and hold time to/from CK rising edge, respectively. The skews, if caused by the fly-by topology,
are compensated by write-leveling.
• In case of LPDDR2 and LPDDR3, the CA[9:0] bus needs to be 90 degree from the CLKP/CLKN signal.
• For DDR3 memory, the memory controller also needs to handle the write leveling required by the interface when
the fly-by topology is applied.
DDR Memory
Data
Width VCCIO DQ DQS
Modules
Types Rank
Chip
Selects
Write
Levelin g
CMD/ADDR
Timin g Fmax
DDR2 8 to 72 bits 1.8V SSTL18 SSTL18D or
SSTL18 UDIMM,
SODIMM,
RDIMM Single, Dual 1, 2 No 2T 400 MHz
8 to 72 bits 1.8V SSTL18 SSTL18D or
SSTL18 Embedded Single, Dual 1, 2 No 2T
3
400 MHz
DDR3 8 to 72 bits 1.5V SSTL15 SSTL15D UDIMM,
SODIMM,
RDIMM Single, Dual 1, 2 Yes 2T
3
400 MHz
8 to 72 bits 1.5V SSTL15 SSTL15D Embedded Single, Dual 1, 2 Yes
1
2T
3
400 MHz
DDR3L 8 to 72 bits 1.35V SSTL135 SSTL135D UDIMM,
SODIMM,
RDIMM Single, Dual 1, 2 Yes 2T
3
400 MHz
8 to 72 bits 1.35V SSTL135 SSTL135D Embedded Single, Dual 1, 2 Yes
1
2T
3
400 MHz
LPDDR2 16 and 32
bits 1.2V HSUL12 HSUL12D Embedded
(Single
Channel) Single 1 No ODDRX2 400 MHz
LPDDR3 16 and 32
bits 1.2V HSUL12 HSUL12D Embedded
(Single
Channel) Single 1 Yes
2
ODDRZ2 400 MHz
1. If Fly-by Wiring is implemented
2. Fly- by wiring is emulated using board traces (Guidelines are in the section below)
3. CSN will use 1T timing