24
ECP5 and ECP5-5G Hi
g
h-Speed I/O Interface
DDR memories also require a Data Mask (DM) signal to mask data bits during write cycles. Note that the ratio of
DQS to data bits is independent of the overall width of the memory. Figure 24 shows a typical 8-bit interface that
has eight associated DQ data bits per DQS strobe signal.
The DDR3 memory module uses fly-by routing topology for the address, command, control and clock signals. This
requires the memory controller to support read and write leveling to adjust for leveled delay on read and write data
transfers. LPDDR3 does not use fly-by routing but write leveling may be supported if user emulates the fly-by rout-
ing using board traces. You can see more information in the DDR pin placement and layout guidelines section of
this document.
One major difference between DDR2/DDR3 and LPDDR2/LPDDR3 is lack of DLL in LPDDR2/LPDDR3 memory
device. This would mean in LPDDR2 and LPDDR3, the clock to data output delay from memory device is not com-
pensated by DLL as in traditional DDR2/DDR3, thus the delay is much larger and has larger spread. Theoretically,
there is no low frequency limitation on LPDDR2/LPDDR3, although most manufactures place a low limit of 10 MHz.
Please note FPGA memory controller side, DLL is still needed to manage write and read phase shift, for all mem-
ory interfaces including LPDDR2 and LPDDR3.
Figure 24. Typical DDR2/DDR3/DDR3L Memory Interface
