25
Status Registers
Status Register System
Status Register System
The hardware status registers are combined to form the
instrument status system. Specific status bits are assigned to
monitor various aspects of the instrument operation and
status. See the following diagram of the status system for
information about the bit assignments and status register
interconnections.
Figure 1
Keysight N9322C Status Register System
Setting and Querying the Status Register
Each bit in a register is represented by a numerical value
based on its location. This number is sent with the
command to enable a particular bit. To enable more than
one bit, send the sum of all of the bits involved.
For example, to enable bit 0 and bit 6 of the standard event
status register, you would send the command
*ESE 65 (1 +
64)
.
Ev
en
t En
ab
le
R
eg
.
7 6 5 4 3 2 1 0
&
&
&
&
&
&
&
+
0
1
2
3
4
5
6
7
Status Byte Register
(*STB?)
Unused
Unused
Error/Event Queue Summary
Unused
Message Available (MAV)
Std. Event Status Sum
Unused
Reserved
+
0
1
2
3
4
5
6
7
Standard Event Status Register
Unused
Unused
Query Error
Dev. Dep. Error
Unused
Command Error
Reserved
Power On
Service Request Enable Register
(*ESE,*ESE?,*ESR?,*)
(*SRE,*SRE?)