Keysight Technologies Infiniium MSOV 084A, Service Manual

Page: 154 / 164

154 Infiniium V-Series Oscilloscopes Service Guide
7
Theory of Operation
The fundamental sample clock is a single-ended 10 GHz signal distributed to each
Oak module and the Wahoo timebase IC through semi-rigid coax. In each case,
the single-ended signal is converted to a differential signal using a bandpass
filtered 180° phase splitter implemented using microwave structures on shielded
inner layers of the PCB.
The Wahoo timebase IC divides the 10 GHz CW clock down into multiple 1 GHz
and 250 MHz clocks. The 1 GHz DigClk clocks are gated by DigRun so that the
ADCs can be synchronized with each other. Wahoo also performs some of the time
interpolator functionality by synchronizing the system trigger to the 1 GHz DigClk
and generating the first two MSBs of the trigger interpolation value.
The 10 GHz SampClk 10G signal is divided down to 1 GHz for use as TbClk and
DigClk. TbClk is divided by four to generate RefClk, which drives the memory
controllers and the calibrator chip. These four 250 MHz outputs are phased in
quadrature to minimize the coupling of sub-harmonics into the DigClk signals. The
RefClk signal that goes to the calibrator chip must be disabled when not in used
by the calibrator system.
Time base circuitry
10 GHz
Clock
Gen
Timbase IC
Ext 10
MHz Ref
TbClk (1GHZ CW)
SysTrig
Nosc[1:0]
RefTrig
DigClk
(1 GHZ Gated)
SampClk[2]
(10GHz CW)
DigRun
Time Base
coax
TbTrig
to calibrator
RefClk
(250MHz CW)
Preamp/
Sampler/
Trigger
Hybrid
PS Filter
ADC
Memory
controller
Splitter
1D
CH4
CH3
Trig[3:2]
2D
4D 4D
Preamp/
Sampler/
Trigger
Hybrid
PS Filter
ADC
Memory
controller
Splitter
1D
CH2
CH1
Trig[1:0]
2D
4D 4D
1D
1S
1S
1:3
Power
Splitter
1S
coax
2S
1S
coax
SampClk[1:0]
(10GHz CW)
Splitter
1D
1D
1D
TbTrigSSTL
1D
Master
4D
3D
1S
1D
2S
(to MSO)
(to interpolator)
(to trigger FPGA)
2D
NC
1D
2D
RefClkSSTL
(250MHz CW)
to MSO
(from trigger)
to acquisition FPGA