8-10
Limit Tests and Digital I/O
Model 6487 Reference Manual
Digital output clear pattern
After every binning operation, the digital output needs to be reset to a clear pattern, which
serves as a “no action” condition for the component handler.
The Model 6487 can be programmed to automatically clear the digital output after the
pass or fail pattern is sent. With auto-clear, you must specify the required pulse width
(delay) for the pass or fail pattern. When not using auto-clear, you must return the digital
output to its clear pattern.
klqb
With the Busy line 4 mode selected, the clear state of line 4 is LO, regardless of
the configured clear pattern. With the /Busy mode selected, the clear state of line
4 is HI.
Auto-Clear timing
— The following example timing diagram (
) and discussion
explain the relationship between the digital output lines for auto-clear.
Figure 8-7
Digital output auto-clear timing example
Initially, the four digital output lines are cleared (in this case, they are all set high). Limit
tests start when the Start-Of-Test (SOT) pulse is received from the component handler.
When the testing process is finished, the pass or fail pattern is applied to the digital output.
As shown in the diagram, lines 2, 3, and 4 go low while line 1 remains high.
The pulse width (delay) of the pass/fail pattern can be set from 0 to 60 sec (10µsec resolu-
tion) as required by the component handler. Note that the delay specifies the pulse width
of line 4. The pulse width of lines 1, 2, and 3 is actually 20µsec longer. Line 4 is skewed
because it is used as the End-Of-Test (EOT) strobe by category register component han-
SOT*
Line 1
Line 2
Line 3
Line 4
(EOT)
10
μ
s
10
μ
s
Delay
* With the SOT line being pulsed low (as shown), /START TEST must be the selected
arm event for the trigger model. If the SOT line is instead pulsed high by the
handler, START TEST must be the selected arm event.
