Read Address
The user logic asserts the
ARVALID
signal only when it drives valid Read address
information. Once asserted,
ARVALID
must remain asserted until the rising clock edge
after the HBM2 controller asserts the
ARREADY
signal. If
ARREADY
is high, the HBM2
controller accepts a valid address that is presented to it. Once calibration is completed
and the HBM2 Controller is ready to accept commands, the
ARREADY
is asserted high.
Read Data Channel
The HBM2 controller asserts the
RVALID
signal when it drives valid read data to the
user logic. The master interface uses the
RREADY
signal to indicate that it accepts the
data. The state of
RREADY
can be always held high, if the master is always able to
accept read data from the HBM2 Controller. The soft logic first in, first out (FIFO)
buffers can be instantiated through the HBM2 parameter editor if the HBM2 controller
expects to ever deassert the
RREADY
signal. The HBM2 controller asserts the
RLAST
signal when it is driving the final read transfer in the burst.
Figure below describes a BL8 Read transaction. The user logic asserts the Read
address (RA0) in T3 using transaction ID
ARID0
, the HBM2 controller
ARREADY
is
already asserted, the READ command is accepted. The controller provides the Read
Data back to the user interface after issuing the READ command to the HBM2 DRAM.
The HBM2 controller asserts the Read data in clock cycle TB. The Read transaction ID
(RID) provided by the HBM2 controller corresponds to the Read Address ID (ARID).
The last piece of the burst 8 transaction (RLAST) is asserted in clock cycle TE.
Figure 19.
AXI Read Transaction
5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
Intel
®
Stratix
®
10 MX HBM2 IP User Guide
39
