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destination asserting the READY signal. Once the source asserts the VALID signal, it

must remain asserted until the handshake occurs, at a rising clock edge at which

VALID and READY are both high. Once the destination asserts READY, it can deassert

READY before the source asserts VALID. The destination can assert READY whenever it

is ready to accept data, or in response to a VALID assertion from the source.

AXI IDs

In an AXI system with multiple masters, the AXI IDs used for the ordering model

include the infrastructure IDs that identify each master uniquely. The ordering model

applies independently to each master in the system.

The AXI ordering model also requires that all transactions with the same ID in the

same direction must provide their responses in the order in which they are issued.

Because the read and write address channels are independent, if an ordering

relationship is required between two transactions with the same ID that are in

different directions, then a master must wait to receive a response to the first

transaction before issuing the second transaction. If a master issues a transaction in

one direction before it has received a response to an earlier transaction in the opposite

direction, there is no ordering guarantee between the two transactions.

AXI Ordering

The AXI system imposes no ordering restrictions between read and write transactions.

Read and write can complete in any order, even if the read address AXI ID (ARID) of a

read transaction is the same as the write address AXI ID (AWID) of a write

transaction. If a master requires a given relationship between a read transaction and a

write transaction, it must ensure that the earlier transaction is completed before it

issues a subsequent transaction. A master can consider the earlier transaction

complete only when one of the following is true:
•

For a read transaction, it receives the last of the read data.

•

For a write transaction, it receives the write response.

5.3.1 AXI Write Transaction

AXI Write Address

You can initiate an AXI write transaction by issuing a valid Write Address signal on the

AXI Write Address Bus. Your user logic should provide the valid write address in the

AWADDR

bus and assert the

AWVALID

to indicate that the address is valid. The master

can assert the

AWVALID

signal only when it drives valid address and control

information.

When the HBM2 controller is ready to accept a Write command transaction, it asserts
the

AWREADY

signal. Address transfer happens when both

AWVALID

and

AWREADY

are

asserted.

5 Intel Stratix 10 MX HBM2 IP Interface

UG-20031 | December 2017

Intel

Stratix

10 MX HBM2 IP User Guide

Summary of Contents for Stratix 10 MX HBM2 IP

Page 1: ...Intel Stratix 10 MX HBM2 IP User Guide Updated for Intel Quartus Prime Design Suite 17 1 Subscribe Send Feedback UG 20031 December 2017 Latest document on the web PDF HTML...

Page 2: ...Design for Synthesis 23 4 Simulating the Intel Stratix 10 MX HBM2 IP 25 4 1 Intel Stratix 10 MX HBM2 IP Example Design 25 4 2 Simulating Intel Stratix 10 MX HBM2 IP with ModelSim 26 4 3 Simulating In...

Page 3: ...ice contains a single universal interface bus per HBM2 interface supporting 8 independent channels The user interface to the HBM2 controller is maintained through the AIX4 protocol Sixteen AXI interfa...

Page 4: ...Figure 2 High Bandwidth Memory Stack of Four DRAM Dies 1 3 Intel Stratix 10 MX HBM2 Features Intel Stratix 10 MX FPGAs offer the following HBM2 features Supports one to eight HBM2 channels per HBM2 i...

Page 5: ...seudo Channels The full rate user interface can operate at a frequency lower than the HBM2 interface frequency For information on supported clock frequencies refer to Intel Stratix 10 MX HBM2 Supporte...

Page 6: ...user logic to the hardened HBM2 controller The following figure shows a high level block diagram of the Intel Stratix 10 HBM2 universal interface bus subsystem The UIB subsystem includes the followin...

Page 7: ...tput from the HBM2 controller through the parameter editor when generating the HBM2 IP HBM2 DRAM The HBM2 DRAM is ideal for high bandwidth operation to multiple DRAM devices across many independent in...

Page 8: ...c temperature sensor The Intel Stratix 10 MX HBM2 IP supports only the Pseudo Channel mode of the HBM2 specification Pseudo Channel mode includes the following features Pseudo Channel mode divides a s...

Page 9: ...M2 Controller Architecture The hardened HBM2 controller provides a controller per Pseudo Channel Each controller consists of a write and read data path and the control logic that helps to translate us...

Page 10: ...per Pseudo Channel You can select the burst transaction mode 32 B vs 64B through the parameter editor The user logic can interface to a maximum of 16 Pseudo Channels 16 AXI ports per HBM2 interface E...

Page 11: ...t it serves every command efficiently Command scheduling The HBM2 controller schedules the incoming commands to achieve maximum efficiency at the HBM2 interface The HBM2 controller also follows the AX...

Page 12: ...cool before again applying power Thermal throttling Thermal throttling is a controller safety feature that helps control thermal runaway if the HBM2 die overheats preventing a catastrophic failure Yo...

Page 13: ...nables the following features by default DBI The DBI option supports both write and read DBI and optimizes SI power consumption by restricting signal switching on the HBM2 DQ bus Parity Supports comma...

Page 14: ...ory HBM2 Interface and launch the parameter editor Figure 6 Selecting High Bandwidth Memory Interface in the IP Catalog UG 20031 December 2017 Intel Corporation All rights reserved Intel the Intel log...

Page 15: ...parameters for your IP General Controller Diagnostics Example Designs 3 2 General Parameters for Intel Stratix 10 MX HBM2 IP The General tab allows you to select the channels that you want to implemen...

Page 16: ...to backpressure the interface Threshold temperature for AXI throttling This parameter defines the temperature in degrees Celsius above which the HBM2 controller throttles AXI interface transactions Th...

Page 17: ...interface frequency Use recommended example design core clock PLL reference clock frequency Automatically calculates the example design core clock PLL reference clock frequency for best performance Di...

Page 18: ...o the HBM2 memory device By choosing the right address reordering configuration you help to improve the efficiency of accesses to the HBM2 memory device based on user traffic pattern The HBMC supports...

Page 19: ...ng allows the controller to postpone refresh commands until there are no pending requests or when it is time to issue a refresh command Select this setting in bandwidth sensitive applications Enable 6...

Page 20: ...ough custom logic connected to the Avalon MM configuration slave port on the traffic generator You can simulate configuration using the example testbench provided in the altera_hbm_tg_axi_tb sv file F...

Page 21: ...ulation when you click Generate Example Design Expect an additional 1 2 minute delay when generating the simulation fileset If you do not enable this parameter the system does not generate simulation...

Page 22: ...og in the Generated HDL Format group box 3 To generate the example design press the Generate Example Design button at the top right of the parameter editor 4 When prompted specify a location at which...

Page 23: ...ample design for synthesis is available under Design Directory hbm_0_example_design qii ed_synth synth ed_synth v The ed_synth_hbm_0_example_design module is the top level design module for the HBM2 I...

Page 24: ...ge_wsi Traffic Generator signals The example design instantiates one traffic generator per AXI4 interface or one Pseudo Channel The traffic generator drives the AXI4 interface signals in the example d...

Page 25: ...ix 10 MX HBM2 IP Generated for Simulation UG 20031 December 2017 Intel Corporation All rights reserved Intel the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos a...

Page 26: ...This command compiles the design files and elaborates the top level design 6 After ld_debug finishes running the Objects window appears In the Objects window select the signals to simulate by right c...

Page 27: ...le the design files and elaborate the top level design 5 Type run all to run the HBM2 simulation 4 5 Simulating Intel Stratix 10 MX HBM2 IP for High Efficiency The default traffic pattern can achieve...

Page 28: ...or High Efficiency Simulation ModelSim Navigate to the project_directory sim ed_sim sim mentor directory open the msim_setup tcl file in an editor and change set TOP_LEVEL_NAME ed_sim ed_sim 4 Simulat...

Page 29: ...VEL_NAME altera_hbm_tg_axi_tb To simulate the design follow the steps in Simulating HBM2 IP with Synopsys VCS Riviera PRO Navigate to the project_directory sim ed_sim aldec directory Open the rivierap...

Page 30: ...l the Intel logo Altera Arria Cyclone Enpirion MAX Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U S and or other countries Intel warrants per...

Page 31: ...RMS at 1e 12 BER 1 22ps at 1e 16 BER You can set the frequencies of the reference clocks in the parameter editor when generating the HBM2 IP Table 13 Intel Stratix 10 MX HBM2 Supported Frequencies Int...

Page 32: ...o channel 0 and Pseudo Channel 1 The signals in the following tables refer to the signal names corresponding to a single AXI port Channel 0 Pseudo Channel 0 Table 15 User Port 0 s AXI4 Write Address C...

Page 33: ...level of the transaction and whether the transaction is a data access or an instruction access 3 b000 No protection axi_0_0_awqos 4 Input Quality of Service The Quality of Service identifier sent for...

Page 34: ...rection Desription axi_0_0_arid 9 Input Read address ID The ID tag for the read address group of signals axi_0_0_araddr 28 29 Input Read address The address of the first transfer in a read burst trans...

Page 35: ...ad address and control information axi_0_0_arready 1 Output Read address ready Indicates that the slave is ready to accept an address and associated control signals Table 19 User Port 0 s Read Data Ch...

Page 36: ...ctions in the five channels use a handshake mechanism for the master and slave to communicate and transfer information Handshake Protocol All five transaction channels use the same VALID READY handsha...

Page 37: ...direction there is no ordering guarantee between the two transactions AXI Ordering The AXI system imposes no ordering restrictions between read and write transactions Read and write can complete in an...

Page 38: ...accepted The master asserts the Write data in clock cycle T3 Because the controller WREADY is already asserted the write data is accepted starting cycle T3 The last piece of the burst 8 transaction i...

Page 39: ...t logic first in first out FIFO buffers can be instantiated through the HBM2 parameter editor if the HBM2 controller expects to ever deassert the RREADY signal The HBM2 controller asserts the RLAST si...

Page 40: ...ation that the core clock frequency and the memory clock frequency are different The following equation represents the HBM2 controller efficiency Efficiency Write transactions Read transactions accept...

Page 41: ...t bus turn around when possible Factors Affecting Controller Efficiency Several factors can affect controller efficiency For best efficiency you should consider these factors in your design User inter...

Page 42: ...Stratix 10 MX device speed grade The maximum core interface frequency is limited by the frequency at which the core logic can meet timing For the best HBM2 efficiency ensure that your user logic foll...

Page 43: ...nductor products to current specifications in accordance with Intel s standard warranty but reserves the right to make changes to any products and services at any time without notice Intel assumes no...

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