6 Intel Stratix 10 MX HBM2 IP Controller Performance
This section discusses key aspects of the HBM2 IP controller performance: efficiency,
latency, and timing.
6.1 Intel Stratix 10 MX HBM2 Bandwidth
For each HBM2 DRAM in an Intel Stratix 10 MX device, there are eight channels of
128-bits each.The following example illustrates the calculation of bandwidth offered
per channel.
Assuming an interface running at 1 GHz:
128 DQ * 1 GHz = 128 Gbps
:
•
The interface operates in double data-rate mode, so the total bandwidth per HBM2
is:
128 Gbps * 2 = 256 Gbps
•
The total bandwidth for the HBM2 interface is:
256 Gbps * 8 = 256
GBytes/sec
•
If the HBM2 controller operates at 90% efficiency, the effective bandwidth is:
256
Gbps * 0.9 = ~230 GByte/sec
6.2 Intel Stratix 10 MX HBM2 IP Efficiency
The efficiency of the Intel Stratix 10 MX HBM2 IP estimates data bus utilization at the
AXI interface.The AXI4 protocol supports independent write and read address and
data channel and accepts concurrent write and read transactions. Calculated efficiency
values take into consideration that the core clock frequency and the memory clock
frequency are different.
The following equation represents the HBM2 controller efficiency:
Efficiency = ((Write transa Read transactions accepted by HBM2
controller)/total valid transaction count) * (core clk frequency/HBM2
interface frequency) * 100
UG-20031 | December 2017
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