Port Name
Width
Direction
Description
axi_0_0_wuser_strb
2
Input
Extra Write Strobes (AXI WUSER port). Indicates
which byte lanes (for u0_wuser_data) hold valid
data, signal is aligned to u0_wstrb.
axi_0_0_wlast
1
Input
Write Last. Indicates the last transfer in a write
burst.
axi_0_0_wvalid
1
Input
Write Valid. Indicates that valid write data and
strobes are available
axi_0_0_wready
1
Output
Write Ready. Indicates that the slave (HBM2
controller) can accept write data.
Table 17.
User Port 0’s Write Response Channel
Port Name
Width
Direction
Description
axi_0_0_bid
9
Output
Response ID Tag. The ID tag of the write
response.
axi_0_0_bresp
2
Output
Write response. Indicates the status of the write
transaction.
• 2'b00 = OKAY; indicates that normal access
is successful.
axi_0_0_bvalid
1
Output
Write response valid. Indicates that the channel
is signaling a valid write response.
axi_0_0_bready
1
Input
Response ready. Indicates that the master can
accept a write response.
Table 18.
User Port 0’s AXI4 Read Address (Command) Channel
Port Name
Width
Direction
Desription
axi_0_0_arid
9
Input
Read address ID. The ID tag for the read
address group of signals.
axi_0_0_araddr
28/29
Input
Read address. The address of the first transfer
in a read burst transaction. This address bus is
28-bits wide for a 4 GB device and 29-bits wide
for an 8 GB device. You must tie the lower-
order five bits to 0.
The system derives the address configuration of
the higher-order bits from the following
information; the order depends on the address
ordering that you choose:
• Bank Address(BA) – 4 bits wide. BA[3:2]
are used as Bank Group(BG) bits
• Row Address(RA) - 14 bits wide.
• Column Address (COL) - 6 bits wide. COL[0]
is tied to 0 for 32B access and COL[1:0] is
tied to 0 for 64B access.
• Stack ID (SID) – 1 bit wide, and applies
only to 8 GB/8H devices. The HBM2
controller uses the SID serves as a higher
order BA bit. The SID is not available in 4
GB devices.
Refer to the Address Ordering section for logical
address mapping details.
axi_0_0_arlen
8
Input
Burst Length. The burst length gives the exact
number of transfers in a burst. The HBMC
supports only one BL4 or BL8 transaction.
• 0b00000000 = Burst length of 1.
continued...
5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
Intel
®
Stratix
®
10 MX HBM2 IP User Guide
34
