AXI Write Data
During a write burst, the master can assert the
WVALID
signal only when it drives
valid write data. Once asserted,
WVALID
must remain asserted until the rising clock
edge after the slave asserts
WREADY
. The master must assert the
WLAST
signal while
it is driving the final write transfer in the burst. User logic must issue the write data in
the same order in which the write addresses are issued.
The following diagram illustrates a BL8 Write transaction. The master asserts the Write
address (WA0) in T1 using transaction ID
AWID0
, the HBM2 controller asserts the
AWREADY
in T2 when the Write command is accepted. The master asserts the Write
data in clock cycle T3. Because the controller
WREADY
is already asserted, the write
data is accepted starting cycle T3. The last piece of the burst 8 transaction is asserted
in clock cycle T6.
Figure 18.
AXI Write Transaction
Write Response Channel
The HBM2 controller uses the Write Response channel to respond on successful Write
trasactions. The slave can assert the
BVALID
signal only when it drives a valid write
response. When asserted,
BVALID
must remain asserted until the rising clock edge
after the master asserts
BREADY
. The default state of
BREADY
can be high, but only if
the master can always accept a write response in a single cycle.
5.3.2 AXI Read Transaction
5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
Intel
®
Stratix
®
10 MX HBM2 IP User Guide
38
