Intel PXA255, Developer'S Manual

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13-18 Intel® PXA255 Processor Developer’s Manual
AC’97 Controller Unit
All data transfers across the AC-link are synchronized to SYNC’s rising edge. The ACUNIT
divides the BITCLK by 256 to generate the SYNC signal. This calculation yields a 48 kHz SYNC
signal, and its period defines a frame. Data is transitioned on AC-link on every BITCLK rising
edge and subsequently sampled on AC-link’s receiving side on each following BITCLK falling
edge. For a timing diagram see Figure 13-3 .
The ACUNIT synchronizes data between two different clock domains: the BITCLK and an internal
system clock. This internal system clock is always half the run mode frequency. The run mode
frequency is equal to or greater than eight times the BITCLK frequency.
13.8 Functional Description
The functional description section applies to all channels.
13.8.1 FIFOs
The ACUNIT has five FIFOs:
•
PCM Transmit FIFO, with sixteen 32-bit entries.
•
PCM Receive FIFO, with sixteen 32-bit entries.
•
Modem Transmit FIFO, with sixteen 32-bit entries (upper 16 bits must always be zero).
•
Modem Receive FIFO, with sixteen 32-bit entries (upper 16 bits are always zero).
•
Mic-in Receive FIFO, with sixteen 32-bit entries (upper 16 bits are always zero).
A receive FIFO triggers a DMA request when the FIFO has eight or more entries. A transmit FIFO
triggers a DMA request when it holds less than eight entries. A transmit FIFO must be half full
(filled with eight entries) before any data is transmitted across the AC-link.
13.8.1.1 Transmit FIFO Errors
Channel-specific status bits are updated during transmit under-run conditions and will trigger
interrupts if enabled. Refer to
Table 13-11 and Table 13-20 for details regarding the status bits.
During transmit under-run conditions, the last valid sample is continuously sent out across the AC-
link. A transmit under-run can occur under the following conditions:
•
Valid transmit data is still available in memory but the DMA controller starves the transmit
FIFO because it is servicing other higher priority peripherals.
•
The DMA controller has transferred all valid data from memory to the transmit FIFO. This
prompts the last valid sample to be echoed across the AC-link until nACRESET is asserted to
turn off the ACUNIT.
13.8.1.2 Receive FIFO Errors
Channel-specific status bits are updated during receive overrun conditions and trigger interrupts
when enabled. Refer to Table 13-12 , Table 13-16 , and Table 13-21 for details regarding the status
bits. During receive over-run conditions, data that the CODEC sends is not recorded.