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15-2

Intel® PXA255 Processor

Developer’s Manual

MultiMediaCard Controller

The MMC bus connects the card stack to the controller. The software and controller can turn the

MMC clock on and off. The card stack and the controller communicate serially through the

command and data lines and implement a message-based protocol. The messages consist of the
following tokens:

•

Command: a 6-byte command token starts an operation. The command set includes card

initialization, card register reads and writes, data transfers, etc. The MMC controller sends the

command token serially on the MMCMD signal. The format for a command token is shown in

Table 15-1

.

•

Response: a response token is an answer to a command token. Each command has either a

specific response type or no response type. The format for a response token varies according to
the response expected and the card’s mode. Response token formats are detailed

The

MultiMediaCard System Specification Version 2.1

.

•

Data: data is transferred serially between the controller and the card in 8-bit blocks at rates up

to 20 Mbps. The format for the data token depends on the card’s mode.

Table 15-2

shows the

data token format for MMC mode and

Table 15-3

shows the data token format for SPI mode.

In MMC mode, all operations contain command tokens and most commands have an associated

response token. Read and write commands also have a data token. Command and response tokens

are sent and received on the bidirectional MMCMD signal and data tokens are sent and received on

Table 15-1. Command Token Format

Bit Position

Width (bits)

Value

Description

47

1

0

start bit

46

1

1

transmission bit

[45:40]

6

x

command index

[39:8]

32

x

argument

[7:1]

7

x

CRC7

0

1

1

end bit

Table 15-2. MMC Data Token Format

Stream Data

Block Data

Description

1

0

start bit

x

x

data

no CRC

x

CRC7

1

1

end bit

Table 15-3. SPI Data Token Format

Value

Description

11111110

start byte

x

data

x

CRC16

«
...
504
505
506
507
508
...
»

Summary of Contents for PXA255

Page 1: ...Intel PXA255 Processor Developer s Manual January 2004 Order Number 278693 002 ...

Page 2: ...ot be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means with...

Page 3: ...dulator PWM 1 5 1 2 17 Interrupt Control 1 5 1 2 18 Network Synchronous Serial Protocol Port 1 5 2 System Architecture 2 1 2 1 Overview 2 1 2 2 Intel XScale Microarchitecture Implementation Options 2 2 2 2 1 Coprocessor 7 Register 4 PSFS Bit 2 2 2 2 2 Coprocessor 14 Registers 0 3 Performance Monitoring 2 3 2 2 3 Coprocessor 14 Register 6 and 7 Clock and Power Management 2 3 2 2 4 Coprocessor 15 Re...

Page 4: ... Manager Sleep Status Register PSSR 3 29 3 5 8 Power Manager Scratch Pad Register PSPR 3 30 3 5 9 Power Manager Fast Sleep Walk up Configuration Register PMFW 3 31 3 5 10 Power Manager GPIO Sleep State Registers PGSR0 PGSR1 PGSR2 3 31 3 5 11 Reset Controller Status Register RCSR 3 33 3 6 Clocks Manager Registers 3 34 3 6 1 Core Clock Configuration Register CCCR 3 34 3 6 2 Clock Enable Register CKE...

Page 5: ...lse Width Modulator Register Locations 4 46 5 DMA Controller 5 1 5 1 DMA Description 5 1 5 1 1 DMAC Channels 5 2 5 1 2 Signal Descriptions 5 2 5 1 3 DMA Channel Priority Scheme 5 3 5 1 4 DMA Descriptors 5 5 5 1 5 Channel States 5 8 5 1 6 Read and Write Order 5 9 5 1 7 Byte Transfer Order 5 9 5 1 8 Trailing Bytes 5 10 5 2 Transferring Data 5 11 5 2 1 Servicing Internal Peripherals 5 11 5 2 2 Quick ...

Page 6: ...ynchronous Static Memory 6 42 6 7 1 Static Memory Interface 6 42 6 7 2 Static Memory SA 1111 Compatibility Configuration Register SA1111CR 6 44 6 7 3 Asynchronous Static Memory Control Registers MSCx 6 46 6 7 4 ROM Interface 6 50 6 7 5 SRAM Interface Overview 6 53 6 7 6 Variable Latency I O VLIO Interface Overview 6 55 6 7 7 FLASH Memory Interface 6 58 6 8 16 Bit PC Card Compact Flash Interface 6 ...

Page 7: ...ters FBRx 7 37 7 6 7 LCD Controller Status Register LCSR 7 38 7 6 8 LCD Controller Interrupt ID Register LIIDR 7 41 7 6 9 TMED RGB Seed Register TRGBR 7 42 7 6 10 TMED Control Register TCR 7 43 7 7 LCD Controller Register Summary 7 44 8 Synchronous Serial Port Controller 8 1 8 1 Overview 8 1 8 2 Signal Description 8 1 8 2 1 External Interface to Synchronous Serial Peripherals 8 1 8 3 Functional De...

Page 8: ... Bytes and Repeated Start Read 1 Byte as a Master 9 20 9 6 5 Read 2 Bytes as a Master Send STOP Using the Abort 9 21 9 7 Glitch Suppression Logic 9 21 9 8 Reset Conditions 9 21 9 9 Register Definitions 9 22 9 9 1 I2C Bus Monitor Register IBMR 9 22 9 9 2 I2C Data Buffer Register IDBR 9 22 9 9 3 I2C Control Register ICR 9 23 9 9 4 I2C Status Register ISR 9 25 9 9 5 I2C Slave Address Register ISAR 9 ...

Page 9: ...B Device Controller 12 1 12 1 USB Overview 12 1 12 2 Device Configuration 12 2 12 3 USB Protocol 12 2 12 3 1 Signalling Levels 12 3 12 3 2 Bit Encoding 12 3 12 3 3 Field Formats 12 4 12 3 4 Packet Formats 12 5 12 3 5 Transaction Formats 12 6 12 3 6 UDC Device Requests 12 8 12 3 7 Configuration 12 9 12 4 UDC Hardware Connection 12 10 12 4 1 Self Powered Device 12 10 12 4 2 Bus Powered Devices 12 12...

Page 10: ...2 45 12 6 17 UDC Endpoint x Data Register UDDR1 6 11 12 46 12 6 18 UDC Endpoint x Data Register UDDR2 7 12 12 46 12 6 19 UDC Endpoint x Data Register UDDR3 8 13 12 47 12 6 20 UDC Endpoint x Data Register UDDR4 9 14 12 47 12 6 21 UDC Endpoint x Data Register UDDR5 10 15 12 48 12 7 USB Device Controller Register Summary 12 48 13 AC 97 Controller Unit 13 1 13 1 Overview 13 1 13 2 Feature List 13 1 13...

Page 11: ...pt Mask Register SAIMR 14 14 14 6 7 Serial Audio Data Register SADR 14 14 14 7 Interrupts 14 15 14 8 I2S Controller Register Summary 14 15 15 MultiMediaCard Controller 15 1 15 1 Overview 15 1 15 2 MMC Controller Functional Description 15 4 15 2 1 Signal Description 15 6 15 2 2 MMC Controller Reset 15 6 15 2 3 Card Initialization Sequence 15 6 15 2 4 MMC and SPI Modes 15 6 15 2 5 Error Detection 15...

Page 12: ...MMC_TXFIFO FIFO 15 37 15 6 MultiMediaCard Controller Register Summary 15 37 16 Network SSP Serial Port 16 1 16 1 Overview 16 1 16 2 Features 16 1 16 3 Signal Description 16 2 16 4 Operation 16 2 16 4 1 Processor and DMA FIFO Access 16 2 16 4 2 Trailing Bytes in the Receive FIFO 16 3 16 4 3 Data Formats 16 3 16 4 4 Hi Z on SSPTXD 16 13 16 4 5 FIFO Operation 16 17 16 4 6 Baud Rate Generation 16 17 1...

Page 13: ... 0x8000_0000 to 0xFFFF FFFF 2 19 2 3 Memory Map Part Two From 0x0000_0000 to 0x7FFF FFFF 2 20 3 1 Clocks Manager Block Diagram 3 3 4 1 General Purpose I O Block Diagram 4 2 4 2 Interrupt Controller Block Diagram 4 21 4 3 PWMn Block Diagram 4 39 4 4 Basic Pulse Width Waveform 4 43 5 1 DMAC Block Diagram 5 1 5 2 DREQ timing requirements 5 3 5 3 No Descriptor Fetch Mode Channel State 5 6 5 4 Descript...

Page 14: ... Bus Master Mode 6 71 6 32 Variable Latency IO 6 71 6 33 Asynchronous Boot Time Configurations and Register Defaults 6 76 6 34 SMROM Boot Time Configurations and Register Defaults 6 77 6 35 SMROM Boot Time Configurations and Register Defaults 6 78 7 1 LCD Controller Block Diagram 7 3 7 2 Temporal Dithering Concept Single Color 7 6 7 3 Compare Range for TMED 7 7 7 4 TMED Block Diagram 7 8 7 5 Palet...

Page 15: ...13 3 13 2 AC 97 Standard Bidirectional Audio Frame 13 4 13 3 AC link Audio Output Frame 13 5 13 4 Start of Audio Output Frame 13 5 13 5 AC 97 Input Frame 13 9 13 6 Start of an Audio Input Frame 13 9 13 7 AC link Powerdown Timing 13 12 13 8 SDATA_IN Wake Up Signaling 13 13 13 9 PCM Transmit and Receive Operation 13 27 13 10 Mic in Receive Only Operation 13 29 13 11 Modem Transmit and Receive Operat...

Page 16: ...ister State 2 6 2 5 Processor Pin Types 2 8 2 6 Pin Signal Descriptions for the PXA255 Processor 2 9 2 7 Pin Description Notes 2 17 2 8 System Architecture Register Address Summary 2 21 3 1 Core PLL Output Frequencies for 3 6864 MHz Crystal 3 5 3 2 95 85 MHz Peripheral PLL Output Frequencies for 3 6864 MHz Crystal 3 5 3 3 147 46 MHz Peripheral PLL Output Frequencies for 3 6864 MHz Crystal 3 6 3 4 ...

Page 17: ...GFER2 Bit Definitions 4 14 4 21 GEDR0 Bit Definitions 4 15 4 22 GEDR1 Bit Definitions 4 15 4 23 GEDR2 Bit Definitions 4 16 4 24 GAFR0_L Bit Definitions 4 17 4 25 GAFR0_U Bit Definitions 4 17 4 26 GAFR1_L Bit Definitions 4 18 4 27 GAFR1_U Bit Definitions 4 18 4 28 GAFR2_L Bit Definitions 4 19 4 29 GAFR2_U Bit Definitions 4 19 4 30 ICMR Bit Definitions 4 22 4 31 ICLR Bit Definitions 4 23 4 32 ICCR B...

Page 18: ...sing 6 19 6 8 External to Internal Address Mapping for SA 1111 Addressing 6 21 6 9 Pin Mapping to SDRAM Devices with Normal Bank Addressing 6 23 6 10 Pin Mapping to SDRAM Devices with SA1111 Addressing 6 25 6 11 SDRAM Command Encoding 6 28 6 12 SDRAM Mode Register Opcode Table 6 28 6 13 SXCNFG Bit Definitions 6 33 6 14 SXCNFG 6 36 6 15 Synchronous Static Memory External to Internal Address Mapping...

Page 19: ...it Definitions 7 34 7 10 LDCMDx Bit Definitions 7 36 7 11 FBRx Bit Definitions 7 37 7 12 LCSR Bit Definitions 7 40 7 13 LIICR Bit Definitions 7 41 7 14 TRGBR Bit Definitions 7 42 7 15 TCR Bit Definitions 7 44 7 16 LCD Controller Register Summary 7 44 8 1 External Interface to Codec 8 1 8 2 SSCR0 Bit Definitions 8 9 8 3 SSCR1 Bit Definitions 8 11 8 4 TFT and RFT Values for DMA Servicing 8 15 8 5 SS...

Page 20: ...12 11 6 ICSR0 Bit Definitions 11 13 11 7 ICSR1 Bit Definitions 11 15 11 8 FICP Register Summary 11 16 12 1 Endpoint Configuration 12 2 12 2 USB States 12 3 12 3 IN OUT and SETUP Token Packet Format 12 5 12 4 SOF Token Packet Format 12 5 12 5 Data Packet Format 12 6 12 6 Handshake Packet Format 12 6 12 7 Bulk Transaction Formats 12 7 12 8 Isochronous Transaction Formats 12 7 12 9 Control Transactio...

Page 21: ...tions 13 26 13 14 PCDR Bit Definitions 13 26 13 15 MCCR Bit Definitions 13 27 13 16 MCSR Bit Definitions 13 28 13 17 MCDR Bit Definitions 13 28 13 18 MOCR Bit Definitions 13 29 13 19 MICR Bit Definitions 13 30 13 20 MOSR Bit Definitions 13 30 13 21 MISR Bit Definitions 13 31 13 22 MODR Bit Definitions 13 31 13 23 Address Mapping for CODEC Registers 13 33 13 24 Register Mapping Summary 13 35 14 1 E...

Page 22: ...it Definitions 16 19 16 4 SSCR1 Bit Definitions 16 21 16 5 SSPSP Bit Definitions 16 23 16 6 SSTO Bit Definitions 16 24 16 7 SSITR Bit Definitions 16 25 16 8 SSSR Bit Definitions 16 26 16 9 SSDR Bit Definitions 16 29 16 10 NSSP Register Address Map 16 29 17 1 UART Signal Descriptions 17 3 17 2 RBR Bit Definitions 17 10 17 3 THR Bit Definitions 17 10 17 4 DLL Bit Definitions 17 11 17 5 Divisor Latch...

Page 23: ...scription March 2003 001 Initial release January 2004 002 Replaced Table 12 13 Modified SSPFRM behavior Added note to Table 3 1 about supported frequencies Explained RDY_sync signal Correct GPIO numbers in Table 4 35 Changed behavior of GPIO pins out of reset Added Polling directions for I2C ...

Page 24: ...xxiv Intel PXA255 Processor Developer s Manual Contents ...

Page 25: ...1 1 Intel XScale Microarchitecture Features The Intel XScale microarchitecture provides these features ARM Architecture Version 5TE ISA compliant ARM Thumb Instruction Support ARM DSP Enhanced Instructions Low power consumption and high performance Intel Media Processing Technology Enhanced 16 bit Multiply 40 bit Accumulator 32 KByte Instruction Cache 32 KByte Data Cache 2 KByte Mini Data Cache 2 ...

Page 26: ... 3 6864 MHz crystal and an optional 32 768 kHz crystal The 3 6864 MHz crystal drives a core Phase Locked Loop PLL and a Peripheral PLL The PLLs produce selected clock frequencies to run particular functional blocks The 32 768 kHz crystal provides an optional clock source that must be selected after a hard reset This clock drives the Real Time Clock RTC Power Management Controller and Interrupt Con...

Page 27: ... AC97 Controller supports AC97 Revision 2 0 CODECs These CODECs can operate at sample rates up to 48 KHz The controller provides independent 16 bit channels for Stereo PCM In Stereo PCM Out Modem In Modem Out and mono Microphone In Each channel includes a FIFO that supports DMA access to memory 1 2 7 Inter IC Sound I2S Controller The I2S Controller provides a serial link to standard I2S CODECs for...

Page 28: ... to the peripherals 1 2 13 UARTs The processor provides three Universal Asynchronous Receiver Transmitters Each UART can be used as a slow infrared SIR transmitter receiver based on the Infrared Data Association Serial Infrared SIR Physical Layer Link Specification 1 2 13 1 Full Function UART FFUART The FFUART baud rate is programmable up to 230 Kbps The FFUART provides a complete set of modem con...

Page 29: ...Hz crystal This crystal can be removed to save system cost The RTC provides a constant frequency output with a programmable alarm register This alarm register can be used to wake up the processor from Sleep mode 1 2 15 OS Timers The OS Timers can be used to provide a 3 68 MHz reference counter with four match registers These registers can be configured to cause interrupts when equal to the referen...

Page 30: ...1 6 Intel PXA255 Processor Developer s Manual Introduction ...

Page 31: ...oint instructions and follows the ARM programmer s model The processor s memory interface supports a variety of memory types to allow design flexibility Support for the connection of two companion chips permits a glueless interface to external devices An integrated LCD display controller provides support for displays up to 640x480 pixels and permits 1 2 4 and 8 bit grayscale and 8 or 16 bit color ...

Page 32: ...User s Manual order number 278793 are defined in the following sections 2 2 1 Coprocessor 7 Register 4 PSFS Bit Bit 5 of this register is defined as the Power Source Fault Status bit or PSFS bit This bit is set when either nVDD_FAULT or nBATT_FAULT pins are asserted and the Imprecise Data Abort Enable IDAE bit in the Power Manager Control Register PMCR is set This is a read only register Ignore re...

Page 33: ...ay be read by software to determine the device type and revision The contents of this register for the Intel PXA255 Processor is defined in the table below Combined this register must read as 0x6905 2X0R where R 0b0000 for the first stepping and then increments for subsequent steppings and X is the revision of the Intel XScale microarchitecture present Please see the Intel Developer Homepage at ht...

Page 34: ...24 Implementation Trademark Implementation trademark 0x69 Intel Corporation 23 16 Architecture Version ARM Architecture version of the core 0x05 ARM Architecture version 5TE 15 13 Core Generation This field is updated when new sets of features are added to the core This allows software that is dependant on core features to target a specific core Core generation 0b001 Intel XScale core 12 10 Core R...

Page 35: ... completed in order the recommended sequence is to insert a load to an unbuffered uncached memory page followed by an operation that depends on data from the load str r1 r2 first store issued ldr r5 r6 load from external unbuffered uncached address r2 if possible mov r5 r5 nop stalls until r5 is loaded str r3 r4 second store completes in program order 2 4 Semaphores The Swap SWP and Swap Byte SWPB...

Page 36: ...be used to recover from runaway code Watchdog reset is disabled by default and must be enabled by software GPIO reset is a soft reset that is less destructive than Hardware and Watchdog resets Each type of reset affects the state of the processor pins Table 2 4 shows each pin s state after each type of reset Leaving Sleep Mode causes a Sleep Mode reset Unlike other resets Sleep Mode resets do not ...

Page 37: ...gh a GPIO the software must first configure the GPIO so that the desired peripheral is connected to its pins The default state of the pins is GPIO inputs To allocate a peripheral to a pin disable the GPIO function for that pin then map the peripheral function onto the pin by selecting the proper alternate function for the pin Some GPIOs have multiple alternate functions After a function is selecte...

Page 38: ... and level of functionality The following modes are supported Turbo Mode low latency nanoseconds switch between two preprogrammed frequencies Run Mode normal full function mode Idle Mode core clocks are stopped resume through an interrupt Sleep Mode low power mode that does not save state but keeps I Os powered The RTC Power Manager and Clock modules are saved except for Coprocessor 14 Note In low...

Page 39: ...nnect to the data output mask enables DQM for SDRAM Driven Low Driven Low nSDRAS OCZ SDRAM RAS output Connect to the row address strobe RAS pins for all banks of SDRAM Driven High Driven High nSDCAS OCZ SDRAM CAS output Connect to the column address strobe CAS pins for all banks of SDRAM Driven High Driven High SDCKE 0 OC Synchronous Static Memory clock enable output Connect to the CKE pins of SMR...

Page 40: ...DY GPIO 18 ICOCZ Variable Latency I O Ready pin input Notifies the memory controller when an external bus device is ready to transfer data Pulled High Note 1 Note 3 L_DD 8 GPIO 66 ICOCZ LCD display data output Transfers pixel information from the LCD Controller to the external LCD panel Memory Controller alternate bus master request input Allows an external device to request the system bus from th...

Page 41: ...ster select output Indicates that the target address on a memory transaction is attribute space Has the same timing as the address bus Pulled High Note 1 Note 5 LCD Controller Pins L_DD 7 0 GPIO 65 58 ICOCZ LCD display data outputs Transfers pixel information from the LCD Controller to the external LCD panel Pulled High Note 1 Note 3 L_DD 8 GPIO 66 ICOCZ LCD display data output Transfers pixel inf...

Page 42: ...PIO 77 ICOCZ AC bias drive output Notifies the panel to change the polarity for some passive LCD panel For TFT panels this signal indicates valid pixel data Pulled High Note 1 Note 3 Full Function UART Pins FFRXD GPIO 34 ICOCZ Full Function UART Receive input MMC chip select 0 output Chip select 0 for the MMC Controller Pulled High Note 1 Note 3 FFTXD GPIO 39 ICOCZ Full Function UART Transmit outp...

Page 43: ...A card enable 2 outputs Selects a PCMCIA card Bit one enables the high byte lane and bit zero enables the low byte lane MMC clock output Clock signal for the MMC Controller Pulled High Note 1 Note 5 L_DD 9 GPIO 67 ICOCZ LCD display data output Transfers pixel information from the LCD Controller to the external LCD panel MMC chip select 0 output Chip select 0 for the MMC Controller Pulled High Note...

Page 44: ...h Note 1 Note 3 NSSPTXD GPIO 83 ICOCZ Network Synchronous Serial Port Transmit Pulled High Note 1 Note 3 NSSPRXD GPIO 84 ICOCZ Network Synchronous Serial Port Receive Pulled High Note 1 Note 3 USB Client Pins USB P IAOAZ USB Client Positive bidirectional Hi Z Hi Z USB N IAOAZ USB Client Negative pin bidirectional Hi Z Hi Z AC97 Controller and I2 S Controller Pins BITCLK GPIO 28 ICOCZ AC97 Audio Po...

Page 45: ...2 ICOCZ General Purpose I O More wakeup sources for sleep mode Pulled High Note 1 Note 3 GPIO 22 21 ICOCZ General Purpose I O Additional General Purpose I O pins Pulled High Note 1 Note 3 Crystal and Clock Pins PXTAL IA 3 6864 Mhz crystal input No external caps are required Note 2 Note 2 PEXTAL OA 3 6864 Mhz crystal output No external caps are required Note 2 Note 2 TXTAL IA 32 Khz crystal input N...

Page 46: ... PXA255 processor to enter sleep mode or force an Imprecise Data Exception which cannot be masked nVDD_FAULT is ignored after a walk up event until the power supply timer completes approximately 10 ms Minimum assertion time for nVDD_FAULT is 1 ms Input Input nRESET IC Hard reset input Level sensitive input used to start the processor from a known address Assertion causes the current instruction to...

Page 47: ...ote 7 VSSN SUP Ground supply for memory bus and PCMCIA pins Must be connected to the common ground plane on the PCB Grounded Grounded Table 2 7 Pin Description Notes Sheet 1 of 2 Note Description 1 GPIO Reset Operation Configured as GPIO inputs by default after any reset The input buffers for these pins are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal res...

Page 48: ...i Z To select the Hi Z state software must set the FS bit in the Power Manager General Configuration Register If PCFR FS is not set then during the transition to sleep these pins function as described in 3 above For nWE nOE and nCS 0 if PCFR FS is not set they are driven high by the Memory Controller before entering sleep If PCFR FS is set these pins are placed in Hi Z 5 PCMCIA Control Pins During...

Page 49: ...MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB 0x8400_0000 0x8800_0000 0x8C00_0000 0x9000_0000 0x9400_0000 0x9800_0000 0x9C00_0000 0xA000_0000 0xA400_0000 0xA800_0000 0xAC00_0000 0xB000_0000 0xB400_0000 0xB800_0000 0xBC...

Page 50: ...served 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Memory Mapped registers LCD Memory Mapped registers Memory Ctl Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB Reserved 64 MB 0x0000_0000 0x0400_0000 0x0800_0000 0x0C00_0000 0x1000_0000 0x1400_0000 0x1800_0000 0x1C00_0000 0x2000_0000 0x2400_0000 0x2800_0000 0x2C00_0000 0x3000_0000 0x3400_0000 0x3800_0000 0x3C00_00...

Page 51: ...ter 0x4000_0100 DRCMR0 Request to Channel Map Register for DREQ 0 0x4000_0104 DRCMR1 Request to Channel Map Register for DREQ 1 0x4000_0108 DRCMR2 Request to Channel Map Register for I2S receive Request 0x4000_010C DRCMR3 Request to Channel Map Register for I2S transmit Request 0x4000_0110 DRCMR4 Request to Channel Map Register for BTUART receive Request 0x4000_0114 DRCMR5 Request to Channel Map R...

Page 52: ...1 Request 0x4000_0190 DRCMR36 Request to Channel Map Register for USB endpoint 12 Request 0x4000_0194 DRCMR37 Request to Channel Map Register for USB endpoint 13 Request 0x4000_0198 DRCMR38 Request to Channel Map Register for USB endpoint 14 Request 0x4000_019C DRCMR39 Reserved 0x4000_0200 DDADR0 DMA Descriptor Address Register Channel 0 0x4000_0204 DSADR0 DMA Source Address Register Channel 0 0x4...

Page 53: ...x4000_0298 DTADR9 DMA Target Address Register Channel 9 0x4000_029C DCMD9 DMA Command Address Register Channel 9 0x4000_02A0 DDADR10 DMA Descriptor Address Register Channel 10 0x4000_02A4 DSADR10 DMA Source Address Register Channel 10 0x4000_02A8 DTADR10 DMA Target Address Register Channel 10 0x4000_02AC DCMD10 DMA Command Address Register Channel 10 0x4000_02B0 DDADR11 DMA Descriptor Address Regi...

Page 54: ...visor Latch Low Register DLAB 1 read write 0x4010_0004 FFDLH Divisor Latch High Register DLAB 1 read write Bluetooth UART 0x4020_0000 0x4020_0000 BTRBR Receive Buffer Register read only 0x4020_0000 BTTHR Transmit Holding Register write only 0x4020_0004 BTIER Interrupt Enable Register read write 0x4020_0008 BTIIR Interrupt ID Register read only 0x4020_0008 BTFCR FIFO Control Register write only 0x4...

Page 55: ...050_0000 POCR PCM Out Control Register 0x4050_0004 PICR PCM In Control Register 0x4050_0008 MCCR Mic In Control Register 0x4050_000C GCR Global Control Register 0x4050_0010 POSR PCM Out Status Register 0x4050_0014 PISR PCM In Status Register 0x4050_0018 MCSR Mic In Status Register 0x4050_001C GSR Global Status Register 0x4050_0020 CAR CODEC Access Register 0x4050_0024 through 0x4050_003C Reserved ...

Page 56: ...oint 3 IN Control Status Register 0x4060_0020 UDCCS4 UDC Endpoint 4 OUT Control Status Register 0x4060_0024 UDCCS5 UDC Endpoint 5 Interrupt Control Status Register 0x4060_0028 UDCCS6 UDC Endpoint 6 IN Control Status Register 0x4060_002C UDCCS7 UDC Endpoint 7 OUT Control Status Register 0x4060_0030 UDCCS8 UDC Endpoint 8 IN Control Status Register 0x4060_0034 UDCCS9 UDC Endpoint 9 OUT Control Status...

Page 57: ...C00 UDDR13 UDC Endpoint 13 Data Register 0x4060_0E00 UDDR14 UDC Endpoint 14 Data Register 0x4060_00E0 UDDR15 UDC Endpoint 15 Data Register 0x4060_0050 UICR0 UDC Interrupt Control Register 0 0x4060_0054 UICR1 UDC Interrupt Control Register 1 0x4060_0058 USIR0 UDC Status Interrupt Register 0 0x4060_005C USIR1 UDC Status Interrupt Register 1 Standard UART 0x4070_0000 0x4070_0000 STRBR Receive Buffer ...

Page 58: ...01C OIER OS Timer Interrupt Enable Register PWM 0 0x40B0_0000 0x40B0_0000 PWM_CTRL0 PWM 0 Control Register 0x40B0_0004 PWM_PWDUTY0 PWM 0 Duty Cycle Register 0x40B0_0008 PWM_PERVAL0 PWM 0 Period Control Register PWM 1 0x40C0_0000 0x40C0_0000 PWM_CTRL1 PWM 1Control Register 0x40C0_0004 PWM_PWDUTY1 PWM 1 Duty Cycle Register 0x40C0_0008 PWM_PERVAL1 PWM 1 Period Control Register Interrupt Control 0x40D...

Page 59: ...50 GEDR2 GPIO Edge Detect Status Register GPIO 80 64 0x40E0_0054 GAFR0_L GPIO Alternate Function Select Register GPIO 15 0 0x40E0_0058 GAFR0_U GPIO Alternate Function Select Register GPIO 31 16 0x40E0_005C GAFR1_L GPIO Alternate Function Select Register GPIO 47 32 0x40E0_0060 GAFR1_U GPIO Alternate Function Select Register GPIO 63 48 0x40E0_0064 GAFR2_L GPIO Alternate Function Select Register GPIO...

Page 60: ...r of blocks for block mode 0x4110_0024 MMC_PRTBUF Partial MMC TXFIFO FIFO written 0x4110_0028 MMC_I_MASK Interrupt Mask 0x4110_002C MMC_I_REG Interrupt Register read only 0x4110_0030 MMC_CMD Index of current command 0x4110_0034 MMC_ARGH MSW part of the current command argument 0x4110_0038 MMC_ARGL LSW part of the current command argument 0x4110_003C MMC_RES Response FIFO read only 0x4110_0040 MMC_...

Page 61: ... High Register DLAB 1 read write LCD Controller 0x4400_0000 0x4400_0000 LCCR0 LCD Controller Control Register 0 0x4400_0004 LCCR1 LCD Controller Control Register 1 0x4400_0008 LCCR2 LCD Controller Control Register 2 0x4400_000C LCCR3 LCD Controller Control Register 3 0x4400_0200 FDADR0 DMA Channel 0 Frame Descriptor Address Register 0x4400_0204 FSADR0 DMA Channel 0 Frame Source Address Register 0x...

Page 62: ...figuration 0x4800_002C MCMEM1 Card interface Common Memory Space Socket 1 Timing Configuration 0x4800_0030 MCATT0 Card interface Attribute Space Socket 0 Timing Configuration 0x4800_0034 MCATT1 Card interface Attribute Space Socket 1 Timing Configuration 0x4800_0038 MCIO0 Card interface I O Space Socket 0 Timing Configuration 0x4800_003C MCIO1 Card interface I O Space Socket 1 Timing Configuration...

Page 63: ...y and the SDRAM clock ratio in the Memory Controller must be set to two If the SDRAM frequency is 99 5 MHz the Memory Frequency is equal to the SDRAM frequency 3 Round the Memory Frequency down to the nearest value of 99 5 MHz L 0x1B 118 0 MHz L 0x20 132 7 MHz L 0x24 147 5 MHz L 0x28 or 165 9 MHz L 0x2D and program the value of L in the Core Clock Configuration register This frequency or half if t...

Page 64: ...ssumed to be doing frequent external memory accesses so running slower is optimum for the best power performance trade off Idle Mode the Core is not being clocked but the rest of the system is fully operational This mode is used during brief lulls in activity when the external system must continue operation but the Core is idle Sleep Mode places the processor in its lowest power state but maintain...

Page 65: ...bus should be clocked as fast as possible For example if a target core frequency of 200 MHz is desired use 200 MHz run mode instead of 200 MHz turbo mode with run at 100 MHz Increasing the PXbus frequency may help reduce the latency involved in accessing non cacheable memory Figure 3 1 Clocks Manager Block Diagram N M 4 DMA Bridge 1 112 UARTs 14 746 AC97 12 288 I2S 5 672 PWM 3 6864 SSP 3 6864 GPIO...

Page 66: ...multipliers Synchronous Serial Port SSP Pulse Width Modulator PWM and the Operating System Timer OST use the 3 6864 MHz oscillator as a reference Out of Hardware Reset the 3 6864 MHz oscillator also drives the RTC and Power Manager PM The user may then enable the 32 768 kHz oscillator which will drive the RTC and PM after it is stabilized The 3 6864 MHz oscillator can be disabled during Sleep Mode...

Page 67: ...the peripheral blocks external interfaces These interfaces require 14 75 MHz UARTs 12 288 MHz AC97 and variable frequencies I2 S The generated frequency may not exactly match the required frequency due to the choice of crystal and the lack of a perfect Least Common Multiple between the units The chosen frequencies Table 3 1 Core PLL Output Frequencies for 3 6864 MHz Crystal L M Turbo Mode Frequenc...

Page 68: ... clock When a module s clock is disabled the registers in that module are still readable and writable The AC97 is an exception and is completely inaccessible if the clock is disabled 3 4 Resets and Power Modes The Clocks and Power Manager Unit determines the processor s Resets Power Sequences and Power Modes Each behaves differently during operation and has specific entry and exit sequences The re...

Page 69: ...easserted Refer to the Intel PXA255 Processor Electrical Mechanical and Thermal Specification for details After the nRESET pin is deasserted the following sequence occurs 1 The 3 6864 MHz oscillator and internal PLL clock generators wait for stabilization 2 The nRESET_OUT pin is deasserted 3 The normal boot up sequence begins All processor units return to their predefined reset conditions Software...

Page 70: ...4 3 1 Invoking GPIO Reset To use the GPIO Reset function set it up through the GPIO Controller The GP 1 pin must be configured as an input and set to its alternate GPIO Reset function in the GPIO Controller The GPIO Reset alternate function is level sensitive and not edge triggered To ensure no spurious resets are generated when the alternate GPIO Reset function is set follow these steps 1 GP 1 mu...

Page 71: ...nRESET_OUT pin is deasserted 3 The normal boot up sequence begins All processor units except the Real Time Clock parts of the Clocks and Power Manager and the Memory Controller return to their predefined reset conditions Software must examine the RCSR to determine the cause for the reset 3 4 4 Run Mode Run Mode is the processor s normal operating mode All power supplies are enabled and all functio...

Page 72: ...o the new mode s proper sequence is followed Idle Sleep Frequency Change Sequence and Reset have precedence over Turbo Mode and cause the processor to exit Turbo Mode When the CPU exits of one of these modes it enters either Run or Turbo Mode based on the state of CCLKCFG TURBO 3 4 6 Idle Mode Idle Mode allows the user to stop the CPU core clock during periods of processor inactivity and continue ...

Page 73: ...o exit Idle Mode exits in the following sequence 1 A valid enabled Interrupt asserts 2 The CPU clocks restart and the CPU resumes operation at the state indicated by CCLKCFG TURBO Idle Mode also exits when the nBATT_FAULT or nVDD_FAULT pin is asserted When either pin is asserted Idle Mode exits in the following sequence 1 The nBATT_FAULT or nVDD_FAULT pin is asserted 2 If the Imprecise Data Abort ...

Page 74: ...ust set FCS in the CCLKCFG See Section 3 7 1 When software sets FCS it may also set or clear other bits in CCLKCFG If software sets the TURBO bit in the same write the CPU enters Turbo Mode when the Frequency Change Sequence exits After software sets the FCS 1 The CPU clock stops and interrupts to the CPU are gated 2 The Memory Controller completes all outstanding transactions in its buffers and f...

Page 75: ...requencies are the same 2 The internal PLL clock generator for the processor clock waits for stabilization Refer to the Intel PXA250 and PXA210 Application Processors Electrical Mechanical and Thermal Specification for details 3 The CPU clocks restart and the CPU resumes operation at the state indicated by the TURBO bit either Run or Turbo Mode Interrupts to the CPU are no longer gated 4 The FCS b...

Page 76: ...r Interrupt controller General purpose I O Clocks and power manager Flash ROM SRAM Unlike normal idle mode in 33 MHz idle mode all other peripheral units cannot be used including SDRAM LCD and DMA controllers 3 4 8 1 Entering 33 MHz Idle Mode During idle mode the processor core clocks stop Before the clocks stop all critical applications must be finished and peripherals turned off If software is e...

Page 77: ...hutdown When Sleep Mode exits the processor s state resets and processing resumes in a boot up mode 3 4 9 1 Sleep Mode External Voltage Regulator Requirements To implement Sleep Mode in the simplest manner the External Voltage Regulator which supplies power to the processor s internal elements must have the following characteristics A power enable input pin that enables the primary supply output c...

Page 78: ...us when the processor attempts to wake up ensure that the chip selects are not set to 0 during sleep mode The PCFR OPDE bit must be cleared to leave the 3 6864 MHz enabled during sleep if the fast walk up sleep configuration is selected by setting the PMFW FWAKE bit PMFW configuration register must be set to select between the standard and fast sleep wakeup configurations Set PMFW FWAKE to 1 to di...

Page 79: ...BATT_FAULT assertion occurred but it is not possible to determine which of the two faults was asserted For either case nVDD_FAULT or nBATT_FAULT assertion software should shut the system down as quickly as possible by performing the steps outlined below to enter Sleep Mode Note All addresses data and instruction used in the abort handler routines should be resident and accessible in the memory pag...

Page 80: ...except valid wake up signals Reset signals and the nBATT_FAULT signal If the nBATT_FAULT signal is asserted while in Sleep Mode GPIO 1 0 are set as the only valid wake up signals The Power Manager watches for wake up events programmed by the CPU before Sleep Mode starts or set by the Power Manager it detects a fault condition In order to detect a rising edge or falling edge on a GPIO pin the risin...

Page 81: ...er for details on configuring the SDRAM interface 11 Software must examine the RCSR to determine what caused the reboot and the Power Manager Sleep Status register PSSR to determine what triggered Sleep Mode 12 If the PSPR was used to preserve any critical states during Sleep Mode software can now recover the information If the nVDD_FAULT or nBATT_FAULT pin is asserted during the Sleep Mode exit s...

Page 82: ...es all outstanding transactions x x x 6 The Memory Controller places SDRAMs in self refresh x x x 7 The PLL is disabled x x x 8 If OPDE and OOK bits are set disable 3 6864 MHz oscillator x x 9 Internal Reset to most modules nRESET_OUT asserted x x 10 PWR_EN is deasserted Power is cut off x x 11 Power to most I O pins is cut off 1 Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAU...

Page 83: ...ESET_OUT x x 12 Restart CPU clocks enable interrupts x x x x x x 1 Fault Sleep Mode starts if IDAE is clear and nBATT_FAULT or nVDD_FAULT is asserted Table 3 5 Power Mode Exit Sequence Table Sheet 2 of 2 Step Description of Action Turbo Run from Turbo Idle Freq Change Sleep Fault 1 Sleep ...

Page 84: ... Buffers VCC Run Turbo R T On T On R On Off On changing Off Off Memory Controller Mem On On On LCD Controller DMA Controller General Periphs PLL On OS timer 3 686 MHz Osc Interrupts Real Time Clock VCC Reg V R 32 768 kHz Osc V On V On V On V On I On Power Manager GP 3 0 PM pads Osc pads HV Batt H B Dynamic Static D S H D H D H D H D H S General IO H KEY T Turbo clock R Run clock V Module powered o...

Page 85: ...he PMCR must be protected through Memory Management Unit MMU permissions This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 3 7 PMCR Bit Definitions 0x40F0_0000 PMCR Clocks and Power Manager Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IDAE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 86: ...written with zeroes 2 FS Float Static Chip Selects during Sleep Mode 0 Static Chip Select pins are not floated in Sleep Mode nCS 5 1 are driven to the state of the appropriate PGSR register bits nCS 1 nWE and nOE are driven high 1 Static Chip Select pins are floated in Sleep Mode The pins nCS 5 0 nWE and nOE are affected Cleared on Hardware Watchdog and GPIO Resets 1 FP Float PCMCIA controls durin...

Page 87: ...gured as inputs during sleep Any GPIO pins that are configured as outputs during sleep should have their associated wake enable bits set to logic zero in all three PMU wake enable registers PWER PRER and PFER This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 3 9 PWER Bit Definitions 0x40F0_000C PWER Clocks and Power Manager Bit 31 30 29 28 27 26 25 24...

Page 88: ... are configured as inputs during sleep Any GPIO pins that are configured as outputs during sleep should have their associated wake enable bits set to logic zero in all three PMU wake enable registers PWER PRER and PFER This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 3 10 PRER Bit Definitions 0x40F0_0010 PRER Clocks and Power Manager Bit 31 30 29 28 ...

Page 89: ...igured as inputs during sleep Any GPIO pins that are configured as outputs during sleep should have their associated wake enable bits set to logic zero in all three PMU wake enable registers PWER PRER and PFER This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 3 11 PFER Bit Definitions 0x40F0_0014 PFER Clocks and Power Manager Bit 31 30 29 28 27 26 25 ...

Page 90: ...DR bits are reset to zero in hardware watchdog and GPIO resets This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 3 12 PEDR Bit Definitions 0x40F0_0018 PEDR Clocks and Power Manager Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 Res...

Page 91: ...GPIO input path but the pull up resisters are not re enabled in this case To clear a status flag write a 1 to it Writing a 0 to a status bit has no effect Hardware watchdog and GPIO resets clear or set the PSSR bits This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 3 13 PSSR Bit Definitions Sheet 1 of 2 0x40F0_0004 PSSR Clocks and Power Manager Bit 31...

Page 92: ...BFS Battery Fault Status 0 nBATT_FAULT pin has not been asserted since it was last cleared by a reset or the CPU 1 nBATT_FAULT pin has been asserted bit is set only after wake up This bit can be set when nBATT_FAULT is asserted while in sleep mode Cleared by hardware watchdog and GPIO resets 0 SSS Software Sleep Status 0 Software has not entered sleep mode through the sleep mode bit since the SSS ...

Page 93: ...ode is required through software or the nBATT_FAULT or nVDD_FAULT pin the contents of the PGSR registers are loaded into the GPIO output data registers that software normally controls through the GPSR and GPCR registers Only pins that are already configured as outputs reflect the new state All bits in the output registers are loaded When the processor re enters the run mode these GPIO pins retain ...

Page 94: ...0 0 0 0 0 0 0 Bits Name Description 31 0 SSx If programmed as an output Sleep state of GPx 0 Pin is driven to a zero during sleep mode 1 Pin is driven to a one during sleep mode Cleared by hardware watchdog and GPIO resets Table 3 17 PGSR1 Bit Definitions 0x40F0_0024 PGSR1 Clocks and Power Manager Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SS63 SS62 S...

Page 95: ...he RCSR status bits for watchdog reset sleep mode and GPIO resets have a hardware reset state of zero This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 3 18 PGSR2 Bit Definitions 0x40F0_0028 PGSR2 Clocks and Power Manager Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SS84 SS83 SS82 SS81 SS80 SS79 SS...

Page 96: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bits Name Description 31 4 reserved 3 GPR GPIO Reset 0 GPIO reset has not occurred since the last time the CPU or hardware reset cleared this bit 1 GPIO reset has occurred since the last time the CPU or hardware reset cleared this bit Cleared by hardware reset and by setting to a 1 2 SMR Sleep Mode 0 Sleep mode has not occurred sin...

Page 97: ...served N M L Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 Bits Name Description 31 10 reserved 9 7 N Run Mode Frequency to Turbo Mode Frequency Multiplier Turbo mode Freq Run mode frequency N 000 reserved 001 reserved 010 Multiplier 1 011 Multiplier 1 5 100 Multiplier 2 101 reserved 110 Multiplier 3 111 reserved Set to 010 on hardware and watchdog resets 6 5 M Memory Frequ...

Page 98: ... 1 1 1 1 Bits Name Description 31 17 reserved 16 CKEN16 LCD Unit Clock Enable 0 Clock to the unit is disabled 1 Clock to the unit is enabled Set by hardware and watchdog resets 15 reserved 14 CKEN14 I2C Unit Clock Enable 0 Clock to the unit is disabled 1 Clock to the unit is enabled Set by hardware and watchdog resets 13 CKEN13 FICP Unit Clock Enable 0 Clock to the unit is disabled 1 Clock to the ...

Page 99: ...rdware and watchdog resets 3 CKEN3 SSP Unit Clock Enable 0 Clock to the unit is disabled 1 Clock to the unit is enabled Set by hardware and watchdog resets 2 CKEN2 AC97 Unit Clock Enable 0 Clock to the unit is disabled 1 Clock to the unit is enabled Set by hardware and watchdog resets 1 CKEN1 PWM1 Clock Enable 0 Clock to the unit is disabled 1 Clock to the unit is enabled Set by hardware and watch...

Page 100: ...ads from reserved bits Write zeros to reserved bits 3 7 Coprocessor 14 Clock and Power Management Coprocessor 14 contains two registers that control the power modes and sequences CP14 register 6 CCLKCFG register CP14 register 7 PWRMODE register Table 3 22 OSCC Bit Definitions 0x4130_0008 OSCC Clocks and Power Manager Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 101: ...unction Data in Rd Instruction Read CCLKCFG MRC p14 0 Rd c6 c0 0 Enter turbo mode TURBO 1 MCR p14 0 Rd c6 c0 0 Enter frequency change sequence FCS 1 Turbo mode bit may be set or cleared in the same write MCR p14 0 Rd c6 c0 0 Enter idle mode M 1 MCR p14 0 Rd c7 c0 0 Enter sleep mode M 3 MCR p14 0 Rd c7 c0 0 Table 3 24 CCLKCFG Bit Definitions CP14 Register 6 CCLKCFG Clocks and Power Manager Bit 31 3...

Page 102: ...l Power On Reset device or another circuit To ensure that the internal ESD protection devices do not activate during power up a minimum rise time must be observed Refer to the Intel PXA255 Processor Electrical Mechanical and Thermal Specification for details 3 8 2 Power Supply Connectivity The processor requires two or three externally supplied voltage levels VCCQ requires 3 3 V 10 VCCN requires 3...

Page 103: ...Note No external capacitors are required 3 8 4 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator The two pairs of crystal pins are located near each other on the processor When crystal oscillators are connected to the pins this proximity leads to low signal swings and slow edges that result in limited noise coupling between the pins If one of the crystal oscillators is replaced b...

Page 104: ...register 0x40F0_0010 PRER Power Manager GPIO Rising edge Detect Enable register 0x40F0_0014 PFER Power Manager GPIO Falling edge Detect Enable register 0x40F0_0018 PEDR Power Manager GPIO Edge Detect Status register 0x40F0_001C PCFR Power Manager General Configuration register 0x40F0_0020 PGSR0 Power Manager GPIO Sleep State register for GP 31 0 0x40F0_0024 PGSR1 Power Manager GPIO Sleep State reg...

Page 105: ...her an input or output When programmed to be an input a GPIO can also serve as an interrupt source All 85 pins are configured as inputs during the assertion of all resets and remain as inputs until they are configured otherwise Use the GPIO Pin Direction Register GPDR to set whether the GPIO pins are outputs or inputs When programmed as an output the pin can be set high by writing to the GPIO Pin ...

Page 106: ... a GPIO pin is used for an alternate function you must still program the proper direction of that pin through the GPDR Details on alternate functions are provided in Section 4 1 2 Figure 4 1 shows a block diagram of a single GPIO pin 4 1 2 GPIO Alternate Functions GPIO pins are capable of having as many as six alternate functions that can be set to enable additional functionality within the proces...

Page 107: ...oller grant GP14 MBREQ ALT_FN_1_IN 01 memory controller alternate bus master request GP15 nCS_1 ALT_FN_2_OUT 10 Active low chip select 1 GP16 PWM0 ALT_FN_2_OUT 10 PWM0 output GP17 PWM1 ALT_FN_2_OUT 10 PWM1 output GP18 RDY ALT_FN_1_IN 01 Ext Bus Ready GP19 DREQ 1 ALT_FN_1_IN 01 External DMA Request GP20 DREQ 0 ALT_FN_1_IN 01 External DMA Request GP23 SCLK ALT_FN_2_OUT 10 SSP Serial Port SSP clock G...

Page 108: ...45 BTRTS ALT_FN_2_OUT 10 UARTs BTUART request to send HWRTS ALT_FN_3_OUT 11 HWUART HWUART request to send GP46 ICP_RXD ALT_FN_1_IN 01 Infrared Communication Port ICP receive data RXD ALT_FN_2_IN 10 UARTs STD_UART receive data GP47 TXD ALT_FN_1_OUT 01 UARTs STD_UART transmit data ICP_TXD ALT_FN_2_OUT 10 Infrared Communication Port ICP transmit data GP48 nPOE ALT_FN_2_OUT 10 Memory Controller Output...

Page 109: ...ller alternate bus master req GP67 LDD 9 ALT_FN_2_OUT 10 LCD Controller LCD data pin 9 MMCCS0 ALT_FN_1_OUT 01 Multimedia Card MMC Controller MMC Chip Select 0 GP68 MMCCS1 ALT_FN_1_OUT 01 Multimedia Card MMC Controller MMC Chip Select 1 LDD 10 ALT_FN_2_OUT 10 LCD Controller LCD data pin 10 GP69 MMCCLK ALT_FN_1_OUT 01 Multimedia Card MMC Controller MMC_CLK LDD 11 ALT_FN_2_OUT 10 LCD Controller LCD d...

Page 110: ..._2_OUT 10 LCD AC Bias GP78 nCS 2 ALT_FN_2_OUT 10 Memory Controller Active low chip select 2 GP79 nCS 3 ALT_FN_2_OUT 10 Memory Controller Active low chip select 3 GP80 nCS 4 ALT_FN_2_OUT 10 Memory Controller Active low chip select 4 GP81 NSSPSCLK ALT_FN_1_IN 01 Network SSP NSSP Serial clock is input NSSPSCLK ALT_FN_1_OUT 01 NSSP Serial clock is output GP82 NSSPSFRM ALT_FN_1_IN 01 NSSP frame is inpu...

Page 111: ...GFER1 GFER2 GEDR Detect Edge Type GEDR0 GEDR1 GEDR2 GAFR Set Alternate Functions GAFR0_L GAFR0_U GAFR1_L GAFR1_U GAFR2_L GAFR2_U NOTE For the alternate function registers the designator _L signifies that the lower 16 GPIOs alternate functions are configured by that register and _U designates that the upper 16 GPIOs alternate functions are configured by that register Table 4 2 GPIO Register Definit...

Page 112: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PL63 PL62 PL61 PL60 PL59 PL58 PL57 PL56 PL55 PL54 PL53 PL52 PL51 PL50 PL49 PL48 PL47 PL46 PL45 PL44 PL43 PL42 PL41 PL40 PL39 PL38 PL37 PL36 PL35 PL34 PL33 PL32 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 0 PL x GPIO Pin Level x where x 32 to 63 This read only field indicates the current ...

Page 113: ...stem Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PD63 PD62 PD61 PD60 PD59 PD58 PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 PD49 PD48 PD47 PD46 PD45 PD44 PD43 PD42 PD41 PD40 PD39 PD38 PD37 PD36 PD35 PD34 PD33 PD32 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 0 PD x GPIO Pin x Direction where...

Page 114: ...0 Bit Definitions Physical Address 0x40E0_0018 GPSR0 System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PS31 PS30 PS29 PS28 PS27 PS26 PS25 PS24 PS23 PS22 PS21 PS20 PS19 PS18 PS17 PS16 PS15 PS14 PS13 PS12 PS11 PS10 PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Des...

Page 115: ... 8 7 6 5 4 3 2 1 0 PC31 PC30 PC29 PC28 PC27 PC26 PC25 PC24 PC23 PC22 PC21 PC20 PC19 PC18 PC17 PC16 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 0 PC x GPIO Pin x Output Pin Clear where x 0 through 31 0 Pin level unaffected 1 If pin configured as an output clear pin level low zero...

Page 116: ...orresponding GRER bit is set causing a GEDR status bit to be set when the pin transitions from logic level zero to logic level one Likewise the GFER is used to set the corresponding GEDR status bit when a transition from logic level one to logic level zero occurs When the corresponding bits are set in both registers either a falling or a rising edge transition causes the corresponding GEDR status ...

Page 117: ...8 7 6 5 4 3 2 1 0 RE63 RE62 RE61 RE60 RE59 RE58 RE57 RE56 RE55 RE54 RE53 RE52 RE51 RE50 RE49 RE48 RE47 RE46 RE45 RE44 RE43 RE42 RE41 RE40 RE39 RE38 RE37 RE36 RE35 RE34 RE33 RE32 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 0 RE x GPIO Pin x Rising Edge Detect Enable where x 32 through 63 0 Disable rising edge detect enable 1 Set corresponding GEDR ...

Page 118: ...7 6 5 4 3 2 1 0 FE63 FE62 FE61 FE60 FE59 FE58 FE57 FE56 FE55 FE54 FE53 FE52 FE51 FE50 FE49 FE48 FE47 FE46 FE45 FE44 FE43 FE42 FE41 FE40 FE39 FE38 FE37 FE36 FE35 FE34 FE33 FE32 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 0 FE x GPIO Pin x Falling Edge Detect Enable where x 32 through 63 0 Disable falling edge detect enable 1 Set corresponding GEDR ...

Page 119: ...System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 0 ED x GPIO Pin x Edge Detect Status wher...

Page 120: ...erforms The function selected is determined by writing the GAFR bit pair as below 00 indicates normal GPIO function 01 selects alternate input function 1 ALT_FN_1_IN or alternate output function 1 ALT_FN_1_OUT 10 selects alternate input function 2 ALT_FN_2_IN or alternate output function 2 ALT_FN_2_OUT 11 selects alternate input function 3 ALT_FN_3_IN or alternate output function 3 ALT_FN_3_OUT Ta...

Page 121: ... is used for its alternate function 1 10 The corresponding GPIO pin GPIO x is used for its alternate function 2 11 The corresponding GPIO pin GPIO x is used for its alternate function 3 Table 4 25 GAFR0_U Bit Definitions Physical Address 0x40E0_0058 GAFR0_U System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AF31 AF30 AF29 AF28 AF27 AF2...

Page 122: ...esponding GPIO pin GPIO x is used for its alternate function 2 11 The corresponding GPIO pin GPIO x is used for its alternate function 3 Table 4 27 GAFR1_U Bit Definitions Physical Address 0x40E0_0060 GAFR1_U System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AF63 AF62 AF61 AF60 AF59 AF58 AF57 AF56 AF55 FA54 AF53 AF52 AF51 AF50 AF49 AF...

Page 123: ...ister determines the corresponding GPIO pin s functionality as one of the alternate functions that is mapped to it or as a generic GPIO pin 00 The corresponding GPIO pin GPIO x is used as a general purpose I O 01 The corresponding GPIO pin GPIO x is used for its alternate function 1 10 The corresponding GPIO pin GPIO x is used for its alternate function 2 11 The corresponding GPIO pin GPIO x is us...

Page 124: ...ion on alternate functions refer to the Source Unit column in Table 4 1 for the appropriate section of this document Table 4 24 through Table 4 29 show the bitmaps of the GPIO Alternate Function registers 4 2 Interrupt Controller The Interrupt Controller controls the interrupt sources available to the processor and also contains the location to determine the first level source of all interrupts It...

Page 125: ...e to find the exact function requesting service When the ICCR DIM bit is zero the Interrupt Mask Register is ignored during Idle mode and all enabled interrupts cause the processor to exit from idle mode Otherwise only unmasked interrupts cause the processor to exit from idle mode The reset state of ICCR DIM is zero Figure 4 2 shows a block diagram of the Interrupt Controller 4 2 2 Interrupt Contr...

Page 126: ...terrupts Table 4 36 describes the available first level interrupts and their location in the ICPR 4 2 2 2 Interrupt Controller Level Register ICLR The ICLR register shown in Table 4 31 controls whether a pending interrupt generates an FIQ or an IRQ interrupt If a pending interrupt is unmasked the corresponding ICLR bit field is decoded to select which processor interrupt is asserted If the interru...

Page 127: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IL31 IL30 IL29 IL28 IL27 IL26 IL25 IL24 IL23 IL22 IL21 IL20 IL19 IL18 IL17 reserved reserved IL14 IL13 IL12 IL11 IL10 IL9 IL8 reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 8 IL x Interrupt Level x where n 8 through 14 and 17 through 31 0 Interrupt routed to IRQ interrupt input 1 Interrupt routed ...

Page 128: ...e unit Table 4 36 describes the available first level interrupts and their location in the ICPR Table 4 33 ICIP Bit Definitions Physical Address 0x40D0_0000 ICIP System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IP31 IP30 IP29 IP28 IP27 IP26 IP25 IP24 IP23 IP22 IP21 IP20 IP19 IP18 IP17 reserved reserved IP14 IP13 IP12 IP11 IP10 IP9 IP...

Page 129: ... 31 IS31 RTC Alarm Match Register Interrupt Pending 0 Interrupt NOT pending due to RTC Alarm Match Register 1 Interrupt pending due to RTC Alarm Match Register 30 IS30 RTC HZ Clock Tick Interrupt Pending 0 Interrupt NOT pending due to RTC HZ Clock Tick 1 Interrupt pending due to RTC HZ Clock Tick 29 IS29 OS Timer Match Register 3 Interrupt Pending 0 Interrupt NOT pending due to OS Timer Match Regi...

Page 130: ...e Request 16 IS16 NETWORK SSP SERVICE REQUEST INTERRUPT PENDING 0 Interrupt NOT pending due to Network SSP Service Request 1 Interrupt pending due to Network SSP Service Request 15 reserved 14 IS14 AC97 Interrupt Pending 0 Interrupt NOT pending due to AC97 unit 1 Interrupt pending due to AC97 unit 13 IS13 I2S Interrupt Pending 0 Interrupt NOT pending due to I2S unit 1 Interrupt pending due to I2S ...

Page 131: ...mer equals match register 2 IS 27 1 OS timer equals match register 1 IS 26 1 OS timer equals match register 0 IS 25 DMA controller 16 DMA Channel service request IS 24 Synchronous Serial Port 3 SSP service request IS 23 MUlti Media Card 9 MMC status error detection IS 22 FFUART 5 x mit receive error in FFUART IS 21 BTUART 5 x mit receive error in BTUART IS 20 STUART 4 x mit receive error in STUART...

Page 132: ...the RTC output clock increments to a pre set value 4 3 1 Real Time Clock Operation The RTC provides a general purpose real time reference for your design The RTC Counter register RCNR is initialized to zero after a hardware reset or a watchdog reset It is a free running counter that starts incrementing the count value after the deassertion of reset The counter is incremented one 32kHz cycle after ...

Page 133: ...ou trim the counter to adjust for inherent inaccuracies in the crystal s frequency and the inaccuracy caused by the division of the 3 6864 MHz oscillator which yields only an approximate 32 kHz frequency The trimming mechanism lets you adjust the RTC to an accuracy of 5 seconds per month The trimming procedure is described in a later paragraph All registers in the RTC with the exception RTTR are r...

Page 134: ...egration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCK reserved DEL CK_DIV Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bits Name Description 31 LCK Locking bit for the trim value 0 RTTR value is allowed to be altered 1 RTTR value is not allowed to be altered 30 26 reserved 25 16 DEL Trim delete count This value represents the num...

Page 135: ...ents or has been written and does not have the two 32 kHz clock cycle delay 4 3 2 4 RTC Status Register RTSR The RTSR shown in Table 4 40 is cleared to all zeroes at hardware reset The ALE and HZE bits enable both the interrupt for the functions as well as the updating the AL and HZ bits The AL and HZ bits are status bits and are set by the RTC logic if the ALE and HZE bits are set respectively Th...

Page 136: ...alue programmed into the RTTR you must first measure the output frequency at the oscillator multiplexor approximately 32 kHz using an accurate time base such as a frequency counter This clock is externally visible by selecting the alternate function for GPIO 12 or GPIO 72 To gain access to the clock program this pin as an output and then switch to the alternate function Refer to Section 4 1 for de...

Page 137: ...pectively is shown in the following equation f1 HZ clock frequency f32k RTC internal clock either the 32 678 kHz crystal output or the 3 68 MHz crystal output divided down to 32 914 kHz RTTR DEL RTTR 25 16 RTTR CK_DIV RTTR 15 0 4 3 3 2 1 Trim Example 1 Measured Value Has No Fractional Component In this example the desired HZ clock frequency is 1 Hz The oscillator output is measured as 36045 000 cy...

Page 138: ...stal oscillators Such factors can include but are not limited to Manufacturing and supplier variance in the crystals Crystal aging effects System voltage differences System manufacturing variance The trim procedure can counteract these factors by providing a highly accurate mechanism to remove the variance and shifts from the manufacturing and static environment variables on an individual system l...

Page 139: ...system services the register 1 The current value of the counter is read 2 An offset is then added to the read value This offset corresponds to the amount of time before the next time out care must be taken to account for counter wraparound 3 The updated value is written back to OSMR3 The OS code must repeat this procedure periodically before each match occurs If a match occurs the OS timer asserts...

Page 140: ... Description 31 0 OSMV OS Timer Match Value The value compared against the OS timer counter Table 4 42 OIER Bit Definitions Physical Address 0x40A0_001C OS Timer Interrupt Enable Register OIER System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved E3 E2 E1 E0 Reset 0 0 0 0 Bits Name Description 31 4 reserved 3 E3 Interrupt enable ...

Page 141: ...the four match registers and the OSCR These bits are set when the match event occurs following the rising edge of the 3 6864 MHz clock and the corresponding interrupt enable bit is set in the OIER The OSSR bits are cleared by writing a one to the proper bit position Writing zeros to this register has no effect Write all reserved bits as zeros and ignore all reads Table 4 43 OWER Bit Definitions Ph...

Page 142: ...riod counter 10 Bit Pulse control A block diagram of one of the PWMs is shown in Figure 4 3 Table 4 45 OSSR Bit Definitions Physical Address 0x40A0_0014 OS Timer Status Register OSSR System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved M3 M2 M1 M0 Reset 0 0 0 0 Bits Name Description 31 4 reserved 3 M3 Match status channel 3 If O...

Page 143: ...ontains one or more fields which determine an attribute of the PWM_OUTn waveform PWM_CTRLn PRESCALE specifies the divisor for the PWM module clock Note that the actual PWM module clock divisor used is 1 greater than the value programmed into PWM_CTRLn PRESCALE This divided PWM module clock drives a 10 bit up counter This up counter feeds 2 separate comparators The first comparator contains the val...

Page 144: ...ion 3 6 2 Clock Enable Register CKEN on page 3 36 If the clock is disabled the unit shuts down in one of two ways Abrupt the PWM stops immediately Graceful the PWM completes the current duty cycle before stopping Shutdown is selected by PWM_CTRL PWM_SD and described in Section 4 5 2 1 4 5 2 Register Descriptions The following paragraphs provide register descriptions for the Pulse Width Modulator 4...

Page 145: ...entire period and is not influenced by the value programmed in the DCYCLE bits Table 4 46 PWM_CTRLn Bit Definitions Physical Address 0x40B0_0000 0x40C0_0000 PWM Control Registers PWM_CTRL0 PWM_CTRL1 System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWM_SD PRESCALE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 146: ...WM cycle to start again Writing all zeroes to this register results in the output maintaining a high state unless FDCYCLE 0x0 and DCYCLE 0x0 If FDCYCLE 0x0 and DCYCLE 0x0 the output maintains a low state regardless of the value in the PV bit field Note Due to internal timing requirements all changes to any of the PWM registers must be complete a minimum of 4 core clock cycles before the start of e...

Page 147: ...e 3 6864 MHz input clock Table 4 48 PWM_PERVALn Bit Definitions Physical Address 0x40B0_0008 0x40C0_0008 PWM Period Control Registers PWM_PERVAL0 PWM_PERVAL1 System Integration Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bits Name Description 31 10 reserved 9 0 PV PW...

Page 148: ...GPIO 80 64 0x40E0_0024 GPCR0 GPIO pin output clear register GPIO 31 0 0x40E0_0028 GPCR1 GPIO pin output clear register GPIO 63 32 0x40E0_002C GPCR2 GPIO pin output clear register GPIO 80 64 0x40E0_0030 GRER0 GPIO rising edge detect enable register GPIO 31 0 0x40E0_0034 GRER1 GPIO rising edge detect enable register GPIO 63 32 0x40E0_0038 GRER2 GPIO rising edge detect enable register GPIO 80 64 0x40...

Page 149: ...0 Table 4 49 GPIO Register Addresses Sheet 2 of 2 Table 4 50 Interrupt Controller Register Addresses Address Name Description 0x40D0_0000 ICIP Interrupt controller IRQ pending register 0x40D0_0004 ICMR Interrupt controller mask register 0x40D0_0008 ICLR Interrupt controller level register 0x40D0_000C ICFP Interrupt controller FIQ pending register 0x40D0_0010 ICPR Interrupt controller pending regis...

Page 150: ...atus register 0x40A0_0018 OWER OS timer watchdog enable register 0x40A0_001C OIER OS timer interrupt enable register Table 4 52 OS Timer Register Addresses Sheet 2 of 2 Table 4 53 Pulse Width Modulator Register Addresses Address Name Description 0x40B0_0000 PWM_CTRL0 PWM0 Control Register 0x40B0_0004 PWM_PWDUTY0 PWM0 Duty Cycle Register 0x40B0_0008 PWM_PERVAL0 PWM0 Period Control Register 0x40C0_0...

Page 151: ...least one memory bus cycle 5 1 DMA Description The DMAC supports only flow through transfers Flow through data passes through the DMAC before the data is latched by the destination in its buffers memory This DMAC can perform memory to memory moves with flow through transfers Figure 5 1 provides an overview of the DMAC Table 5 1 provides a list of the DMAC signals and descriptions Figure 5 1 DMAC B...

Page 152: ...further detail in Section 5 1 4 Software must ensure cache coherency when it configures the DMA channels The DMAC does not check the cache so target and source addresses must be configured as non cacheable in the Memory Management Unit Each demand for data that a peripheral generates results in a read or write to memory data A peripheral must not request a DMA transfer unless it is prepared to rea...

Page 153: ...upts on a channel such as ENDIRQEN STARTIRQEN and STOPIRQEN When DMA interrupt occurs it is visible in Pending Interrupt Register Bit 25 see Section 4 2 2 5 Interrupt Controller Pending Register ICPR on page 4 25 When a pending interrupt becomes active it is sent to the CPU if its corresponding ICMR mask Bit 25 see Section 4 2 2 1 Interrupt Controller Mask Register ICMR on page 4 22 is set to a on...

Page 154: ...s are running concurrently The channels get a round robin priority in each set Out of reset the state machine state is zero If a channel in set zero has a pending request that channel is serviced If a channel in set one has a pending request that channel is serviced and so on Once a request is serviced the state machine Table 5 2 Channel Priority if all channels are running concurrently Set Channe...

Page 155: ...ADRx and DCMDx registers When the Run bit is set the DMAC immediately begins to transfer data No Descriptor fetches are performed at the beginning of the transfer The channel stops when it finishes the transfer Ensure that the software does not program the channel s DDADx No Descriptor Fetch Mode A typical No Descriptor Fetch Mode DCSR NODESCFETCH 1 operation follows 1 The channel is in an uniniti...

Page 156: ...CH 0 operation follows 1 The channel is in an uninitialized state after reset 2 The software writes a descriptor address aligned to a 16 byte boundary to the DDADR register 3 The software writes a 1 to the DCSR RUN bit 4 The DMAC fetches the four word descriptor assuming that the memory is already set up with the descriptor chain from the memory indicated by DDADR 5 The four word DMA descriptor al...

Page 157: ...ith a new descriptor fetch from the memory as determined by the DDADR STOP bit Bit 0 STOP of Word 0 in a DMA descriptor the low bit of the DDADRx field marks the descriptor at the end of a descriptor list The value of the STOP bit does not affect the manner in which the channel s registers load the descriptor s fields If a descriptor with its STOP bit set is loaded into a channel s registers the c...

Page 158: ... and DCSRx STOPSTATE are both set If they are then software must clear the DCSRx RUN bit and re initialize the DMA channel 5 1 5 Channel States A DMA channel can go through any of the following states Uninitialized Channel is in an uninitialized state after reset Valid Descriptor Not Running Software has loaded a descriptor in the DDADR of the channel in the Descriptor Fetch Mode or has programmed...

Page 159: ...s to function correctly see Example 4 on page 5 27 It also allows schemes in which a DMA stream writes data blocks followed by status blocks and schemes in which another DMA stream probably from the processor polls the same field in the status block The DMAC ensures that data is not retained in per channel buffers between descriptors When a descriptor is completely processed any read data that is ...

Page 160: ...es equal to the smaller of DCMD LENGTH or DCMD SIZE Companion Chip Related Transfers The companion chip must assert the request if the DMAC must handle the trailing bytes If the request is asserted the DMA transfers a number of bytes equal to the smaller of DCMD LENGTH or DCMD SIZE Memory to Internal Peripheral Transfers Most peripherals send a request for trailing bytes during memory to internal ...

Page 161: ... Main memory includes any memory that the processor supports except writes to flash Writes to flash are not supported and cause a bus error In flow through transfer mode data passes through the DMAC before it is latched by the destination in its buffers memory The DMAC can also perform memory to memory moves in flow through transfer mode 5 2 1 Servicing Internal Peripherals The DMAC provides the D...

Page 162: ...ter bits DSADR SRCADDR external memory address DTADR TRGADDR internal peripheral s address DCMD INCSRCADDR 1 DCMD FLOWSRC 0 DCMD FLOWTRG 1 5 2 1 2 Using Flow Through DMA Write Cycles to Service Internal Peripherals A flow through DMA write for an internal peripheral begins when the internal peripheral sends a request via the PREQ bus to a DMAC channel that is running and configured for a flow thro...

Page 163: ...ransmit 0x4010_0000 1 01 8 16 32 or trailing Target 0x4000_011c AC97 microphone 0x4050_0060 4 11 8 16 32 Source 0x4000_0120 modem receive 0x4050_0140 4 11 8 16 32 Source 0x4000_0124 modem transmit 0x4050_0140 4 11 8 16 32 Target 0x4000_0128 audio receive 0x4050_0040 4 11 8 16 32 Source 0x4000_012c audio transmit 0x4050_0040 4 11 8 16 32 Target 0x4000_0130 SSP receive 0x4100_0010 2 10 8 16 Source 0...

Page 164: ...or to wait for the request before it initiates the transfer If DCMDx IRQEN is set to a 1 a DMA interrupt can be requested at the end of the last cycle associated with the byte that caused DCMDx LENGTH to decrease from a 1 to a 0 USB endpoint 1 transmit 0x4060_0100 1 01 32 Target 0x4000_0164 endpoint 2 receive 0x4060_0180 1 01 32 Source 0x4000_0168 endpoint 3 transmit 0x4060_0200 1 01 32 Target 0x4...

Page 165: ...nt in the external address For a flow through DMA read to an external peripheral use the following settings for the DMAC register bits DSADR SRCADDR external memory address DTADR TRGADDR companion chip s address DCMD INCSRCADDR 1 DCMD INCTRGADDR 0 DCMD FLOWSRC 0 DCMD FLOWTRG 1 5 2 3 2 Using Flow Through DMA Write Cycles to Service External Peripherals A flow through DMA write to an external periph...

Page 166: ... channel configured for the move fetches the four word descriptor The channel transfers data without waiting for PREQ or DREQ to be asserted The smaller value of DCMDx SIZE or DCMDx LENGTH specifies the number of bytes to be transferred 3 The DMAC sends a request to the memory controller to read the number of bytes addressed by DSADRx 31 0 into a 32 byte staging buffer in the DMAC 4 The DMAC gener...

Page 167: ...ter Ignore reads from reserved bits Write zeros to reserved bits 5 3 2 DMA Channel Control Status Register DCSRx The DCSRx shown in Table 5 7 contains the control and status bit for each channel Read this register to find the source of an interrupt Write the read value back to the register to clear the interrupt This is a read write register Ignore reads from reserved bits Write zeros to reserved ...

Page 168: ...d channel After clearing the run bit to stop the channel an end interrupt is not guaranteed to happen if the length bits DCMDx LENGTH is zero Software must determine if the transfer is done after clearing the run bit 30 NODESC FETCH No Descriptor Fetch read write 0 Descriptor Fetch Mode 1 No Descriptor Fetch Mode Determines if the channel has a descriptor If this bit is set to a 0 the channel is i...

Page 169: ...pt to occur Software must write a 1 to this bit to reset the corresponding interrupt Writing a 0 to this bit has no effect 0 BUSERR INTR Bus Error Interrupt read write 0 no interrupt 1 bus error caused interrupt Indicates that there was an error while transferring data An error during data transfer occurs when the channel has a bad descriptor source or target address An address is considered bad w...

Page 170: ...iptor Fetch Mode Table 5 8 DRCMRx Bit Definitions Physical Address 0x4000_0100 0x4000_019C DMA Request to Channel Map Register DRCMRx DMA Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAPVLD reserved CHLNUM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 8 reserved 7 MAPVLD Map Valid read...

Page 171: ... are reserved DSADR cannot contain the address of any other internal DMA LCD or MEMC registers This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 5 9 DDADRx Bit Definitions 0x4000_02x0 DMA Descriptor Address Register DDADRx DMA Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DESCRIPTOR ADDRESS reserv...

Page 172: ... must be 32 bit aligned so that bits 1 0 are reserved DTADRx must not contain the address of any other internal DMA LCD or MEMC register The DTADRx must not contain a flash address because writes to flash from the DMAC are not supported This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 5 10 DSADRx Bit Definitions 0x4000_02x4 DMA Source Addr Register D...

Page 173: ...rved bits Write zeros to reserved bits Table 5 11 DTADRx Bit Definitions 0x4000_02x8 DMA Target Addr Register DTADRx DMA Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TARGET ADDRESS reserved Reset Uninitialized Bits Name Description 31 3 TRGADDR Target Address read write Address of the on chip peripheral or the address of a memory location Add...

Page 174: ...ource read write 0 Start the data transfer immediately 1 Wait for a request signal before initiating the data transfer Indicates the flow control of the source This bit must be 1 if the source is an onchip or external peripheral If either the DCMD FLOWSRC or DCMD FLOWTRG bit is set the current DMA does not initiate a transfer until it receives a request Do not set both the DCMD FLOWTRG and DCMD FL...

Page 175: ...ransfer in bytes read write Indicates the length of transfer in bytes DCMD LENGTH 0 means zero bytes for Descriptor Fetch Mode only DCMD LENGTH 0 is an invalid setting for the No Descriptor Fetch Mode The maximum transfer length is 8K 1 bytes If the transfer involves any of the internal peripherals the length of the transfer must be an integer multiple of the width of that peripheral Table 5 12 DC...

Page 176: ...a channel that is running Allocate a new descriptor and make it an end descriptor whose ddadr field points back at itself newDesc New Desc newDesc ddadr newDesc STOP make it a zero length descriptor newDesc dcmd ZERO Start the channel DMANEXT CHAN newDesc DRUN 1 The channel starts loads the descriptor in its registers and stops because the transfer length is 0 and the STOP bit is set No data is tr...

Page 177: ...or some applications while a non descriptor based DMA is best for others For applications that can not tolerate the time needed to fetch a descriptor before each DMA transfer choose the non descriptor based DMA method For applications that can tolerate it a descriptor based DMA method can reduce the amount of core intervention Self Modifying Descriptors The descriptor based DMA system can be used ...

Page 178: ... Description 0x4000_0000 DCSR0 DMA Control Status Register for Channel 0 0x4000_0004 DCSR1 DMA Control Status Register for Channel 1 0x4000_0008 DCSR2 DMA Control Status Register for Channel 2 0x4000_000C DCSR3 DMA Control Status Register for Channel 3 0x4000_0010 DCSR4 DMA Control Status Register for Channel 4 0x4000_0014 DCSR5 DMA Control Status Register for Channel 5 0x4000_0018 DCSR6 DMA Contr...

Page 179: ... Request 0x4000_0138 DRCMR14 Request to Channel Map Register for SSP transmit Request 0x4000_013C DRCMR15 reserved 0x4000_0140 DRCMR16 reserved 0x4000_0144 DRCMR17 Request to Channel Map Register for FICP receive Request 0x4000_0148 DRCMR18 Request to Channel Map Register for FICP transmit Request 0x4000_014C DRCMR19 Request to Channel Map Register for STUART receive Request 0x4000_0150 DRCMR20 Re...

Page 180: ... DCMD0 DMA Command Address Register channel 0 0x4000_0210 DDADR1 DMA Descriptor Address Register channel 1 0x4000_0214 DSADR1 DMA Source Address Register channel 1 0x4000_0218 DTADR1 DMA Target Address Register channel 1 0x4000_021C DCMD1 DMA Command Address Register channel 1 0x4000_0220 DDADR2 DMA Descriptor Address Register channel 2 0x4000_0224 DSADR2 DMA Source Address Register channel 2 0x40...

Page 181: ...D9 DMA Command Address Register channel 9 0x4000_02A0 DDADR10 DMA Descriptor Address Register channel 10 0x4000_02A4 DSADR10 DMA Source Address Register channel 10 0x4000_02A8 DTADR10 DMA Target Address Register channel 10 0x4000_02AC DCMD10 DMA Command Address Register channel 10 0x4000_02B0 DDADR11 DMA Descriptor Address Register channel 11 0x4000_02B4 DSADR11 DMA Source Address Register channel...

Page 182: ... 0x4000_02F0 DDADR15 DMA Descriptor Address Register channel 15 0x4000_02F4 DSADR15 DMA Source Address Register channel 15 0x4000_02F8 DTADR15 DMA Target Address Register channel 15 0x4000_02FC DCMD15 DMA Command Address Register channel 15 Table 5 13 DMA Controller Register Summary Sheet 5 of 5 Address Name Description ...

Page 183: ...ernal memory bus interface supports Synchronous Dynamic Memory SDRAM synchronous and asynchronous burst modes Page mode flash Synchronous Mask ROM SMROM Page Mode ROM SRAM SRAM like Variable Latency I O VLIO 16 bit PC Card expansion memory and Compact Flash Memory types can be programmed through the Memory Interface Configuration registers Figure 6 1 is a block diagram of the maximum configuration...

Page 184: ...titions are divided into two Figure 6 1 General Memory Interface Configuration Memory Controller Interface SDRAM Partition 0 SDRAM Partition 1 SDRAM Partition 2 SDRAM Partition 3 nSDCS 0 nSDCS 1 nSDCS 2 nSDCS 3 nCS 0 nCS 1 nCS 2 nCS 3 nCS 4 nCS 5 Static Bank 3 Static Bank 4 Static Bank 5 Buffers and Transceivers DQM 3 0 nSDRAS nSDCAS SDCLK 2 SDCKE 1 SDCLK 1 SDCKE 1 SDCLK 0 MD 31 0 MA 25 0 Card Con...

Page 185: ...6 is sent to the SDRAM devices by writing to the MDMRS register The PXA255 processor adds support for low power SDRAM by giving software access to the Extended Mode Register via the MDMRSLP register MRS commands always configure SDRAM internal mode registers for sequential burst type and a burst length of four The CAS latency is determined by the DTC0 or DTC2 field of MDCNFG 6 2 2 Static Memory In...

Page 186: ...ease 2 1 and CF and CompactFlash Specification Revision 1 4 The 16 bit PC Card Compact Flash interface provides control signals to support any combination of 16 bit PC Card Compact Flash for two card sockets using address line MA 25 0 and data lines MD 15 0 The processor 16 bit PC Card Compact Flash Controller provides the following signals nPREG is muxed with MA 26 and selects register space I O ...

Page 187: ...KE nWE addr 11 0 BA 1 0 DQML DQMH DQ 15 0 4Mx16 SDRAM nCS nRAS nCAS CLK CKE nWE addr 11 0 BA 1 0 DQML DQMH DQ 15 0 4Mx16 SDRAM nCS nRAS nCAS CLK CKE nWE addr 11 0 BA 1 0 DQML DQMH DQ 15 0 4Mx16 SDRAM nCS nRAS nCAS CLK CKE nWE addr 11 0 BA 1 0 DQML DQMH DQ 15 0 MD 31 0 DQM 3 0 MA 23 10 SDCLK 2 1 nSDRAS nSDCAS nWE CKE 1 nSDCS 2 0 0 0 1 1 2 2 1 1 1 1 2 2 21 10 23 22 15 0 31 16 0 3 2 31 16 31 16 15 0 ...

Page 188: ...R addr 12 0 DQML DQMH DQ 15 0 2Mx16 SMROM nCS nRAS nCAS CLK CKE nMR addr 12 0 DQML DQMH DQ 15 0 SRAM nCS nOE nWE addr 20 0 DQML DQMH DQ 15 0 2Mx16 SMROM nCS nRAS nCAS CLK CKE nMR addr 12 0 DQML DQMH DQ 15 0 2Mx16 SMROM nCS nRAS nCAS CLK CKE nMR addr 12 0 DQML DQMH DQ 15 0 SRAM nCS nOE nWE addr 20 0 DQML DQMH DQ 15 0 MD 31 0 nOE MA 22 2 SDCLK 0 nSDRAS nSDCAS nWE CKE 0 nCS 2 0 0 0 1 1 2 2 15 0 31 16...

Page 189: ...ach write access to Flash memory space must take place in one non burst operation regardless of the bus size Table 6 1 Device Transactions Bus Operation Burst Size Words Start Address Bits 4 2 Description Read single 1 Any Generated by core DMA or LCD request Read burst 4 0 4 Generated by DMA or LCD request Read burst 8 0 Generated by cache line fills Write single 1 Any 1 4 bytes are written as sp...

Page 190: ... unoccupied portion are processed as if the memory occupies the entire 64 MB of the memory partition A single word or half word if the data bus width is defined as 16 bits access to a disabled SDRAM partition MDCNFG DEx 0 causes a CBR refresh cycle to all four partitions This technique is used in the hardware initialization procedure Read return data is indeterminate and writes are not executed on...

Page 191: ...le to all partitions When all partitions are disabled the refresh counter is disabled 0 SDRAM partition disabled 1 SDRAM partition enabled 1 DE1 SDRAM enable for partition 1 For each SDRAM partition there is an enable bit A single non burst 32 bit or 16 bit if MDCNFG DWID0 1 access read or write to a disabled SDRAM partition triggers a CBR refresh cycle to all partitions When all partitions are di...

Page 192: ...this bit will override the addressing bit programmed in MDCNFG DADDR0 For an explanation on how the SA1111 addressing works see Table 6 8 15 13 reserved 16 DE2 SDRAM enable for partition 2 For each SDRAM partition there is an enable bit A single non burst 32 bit or 16 bit if MDCNFG DWID2 1 access read or write to a disabled SDRAM partition triggers a CBR refresh cycle to all partitions When all pa...

Page 193: ...SDCLKs SDCLKs may not be equivalent to memory clocks based on the MDREFRx KxDB2 See Figure 6 5 for a description of these timing numbers 26 DADDR2 reserved For an explanation on how the alternate addressing works see Figure 6 4 27 DLATCH2 Return Data from SDRAM latching scheme for pair 2 3 0 Latch return data using fixed delay from MEMCLK 1 Latch return data with return clock This bit must always ...

Page 194: ...to transfer the required amount of data For example during a cache line fill the controller can perform a four beat burst followed immediately by another four beat burst This approach requires the controller to generate the first address for the second burst During transfer cycles less than four beats the controller ignores the data it does not need For instance if the SDRAM is configured as non c...

Page 195: ...MRSLP MDLPENx bit is set To write a new low power MRS value to SDRAM first enable the memory via the MDCNFG register and then write the MDMRSLP register with the enable bits set This register is not used with in the processor except to write the value during the MRS command All values in the MDCNFG register must be programmed correctly to ensure proper operation of the SDRAM The register is used b...

Page 196: ...e following conditions determine whether SDRAM refreshes occur No refreshes are sent to SDRAM when the refresh counter is cleared to zero If a single transaction to a disabled SDRAM partition is requested a refresh to all four partitions is performed If all four SDRAM partitions are disabled the refresh counter is disabled If the clock frequency is changed the register must be rewritten even if th...

Page 197: ...tatus bit for entering and exiting SDRAM self refresh and is automatically set on a hardware or sleep reset 0 Self refresh disabled 1 Self refresh enabled SLFRSH can be set by software to force a self refresh command E1PIN does not have to be cleared The appropriate clock run bits K1RUN and or K2RUN must remain set until SDRAM has entered self refresh and must be set prior to exiting self refresh ...

Page 198: ... Control Status 0 SDCKE1 is disabled 1 SDCKE1 is enabled E1PIN can be cleared by program to cause a power down command if K1RUN 1 and or K2RUN 1 and SLFRSH 0 Use with caution because the resulting state prohibits automatic transitions for mode register set read write and refresh commands E1PIN can be set by program to cause a power down exit command if K1RUN 1 and or K2RUN 1 and SLFRSH 0 Setting E...

Page 199: ... command and read commands E0PIN can be set by the program to cause a power down exit command if K0RUN 1 11 0 DRI SDRAM refresh interval all partitions The number of memory clock cycles divided by 32 between auto refresh CBR cycles One row is refreshed in each SDRAM bank during each CBR refresh cycle This interval is applicable to all SDRAM in the four partitions To calculate the refresh interval ...

Page 200: ...M Addressing Modes The processor supports two addressing modes Normal Bank Address mode and SA 1111 Address mode The addressing mode alters the order of the address bits that are driven on the individual memory address pins and control the SDRAM components Refer to Table 6 7 through Table 6 9 for a listing of address mapping options Table 6 6 Sample SDRAM Memory Size Options SDRAM Configuration Wo...

Page 201: ...1 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1x11x8x32 21 20 19 18 17 16 15 14 13 12 11 10 21 0 9 8 7 6 5 4 3 2 1x11x8x16 20 19 18 17 16 15 14 13 12 11 10 9 20 0 8 7 6 5 4 3 2 1 1x11x9x32 22 21 20 19 18 17 16 15 14 13 12 11 22 0 10 9 8 7 6 5 4 3 2 1x11x9x16 21 20 19 18 17 16 15 14 13 12 11 10 21 0 9 8 7 6 5 4 3 2 1 1x11x10x32 23 22 21 20 19 18 17 16 15 14 13 12 2...

Page 202: ... 21 20 19 18 17 16 15 14 13 12 11 10 22 21 0 9 8 7 6 5 4 3 2 1 2x11x10x32 24 23 22 21 20 19 18 17 16 15 14 13 12 24 23 0 11 10 9 8 7 6 5 4 3 2 2x11x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 23 22 0 10 9 8 7 6 5 4 3 2 1 2x11x11x32 NOT VALID illegal addressing combination NOT VALID illegal addressing combination 2x11x11x16 NOT VALID illegal addressing combination NOT VALID illegal addressing comb...

Page 203: ...ng combination NOT VALID illegal addressing combination 1x11x9x32 21 20 19 18 17 16 15 14 13 12 11 10 21 0 22 9 8 7 6 5 4 3 2 1x11x9x16 21 20 19 18 17 16 15 14 13 12 11 10 21 0 9 8 7 6 5 4 3 2 1 1x11x10x32 21 20 19 18 17 16 15 14 13 12 11 10 21 0 23 22 9 8 7 6 5 4 3 2 1x11x10x16 21 20 19 18 17 16 15 14 13 12 11 10 21 0 22 9 8 7 6 5 4 3 2 1 1x11x11x32 NOT VALID illegal addressing combination NOT VA...

Page 204: ...3 9 8 7 6 5 4 3 2 2x11x9x16 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 0 9 8 7 6 5 4 3 2 1 2x11x10x32 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 0 24 23 9 8 7 6 5 4 3 2 2x11x10x16 22 21 20 19 18 17 16 15 14 13 12 11 10 22 21 0 23 9 8 7 6 5 4 3 2 1 2x11x11x32 NOT VALID illegal addressing combination NOT VALID illegal addressing combination 2x11x11x16 NOT VALID illegal addressing combination NOT...

Page 205: ...nternal Address Mapping for SA 1111 Addressing Sheet 3 of 3 Bits Bank x Row x Col x Data External Address pins at SDRAM RAS Time MA 24 10 External Address pins at SDRAM CAS Time MA 24 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Table 6 9 Pin Mapping to SDRAM Devices with Normal Bank Addressing Sheet 1 of 3 Bits Bank x Row x Col x Data Pin mapping to...

Page 206: ... A4 A3 A2 A1 A0 2x11x8x16 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x9x32 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x9x16 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x10x32 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x10x16 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x11x32 NOT VALID illegal addressing combination 2x11x11x16 NOT VALID illegal addressing combination 2x12x8x32 BA1 BA0 ...

Page 207: ...gnals driven from the PXA255 processor MA24 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 1x11x8x32 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1x11x8x16 NOT VALID illegal addressing combination 1x11x9x32 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1x11x9x16 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1x11x10x32 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1x11x10x16 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2...

Page 208: ...1 A0 2x11x8x16 NOT VALID illegal addressing combination 2x11x9x32 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x9x16 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x10x32 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x10x16 BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x11x11x32 NOT VALID illegal addressing combination 2x11x11x16 NOT VALID illegal addressing combination 2x12x8x32 BA1 BA0 A11 A10 A9 A...

Page 209: ...ddressing combination 2x12x11x16 NOT VALID illegal addressing combination 2x13x8x32 A12 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x13x8x16 NOT VALID illegal addressing combination 2x13x9x32 A12 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x13x9x16 A12 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x13x10x32 NOT VALID too big 2x13x10x16 A12 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2x13x...

Page 210: ... at clk n 1 SDCKE at clk n nSDCS 3 0 nSDRAS nSDCAS nWE DQM 3 0 MA 24 10 24 23 22 21 20 19 10 PWRDN 1 0 1 1 1 1 1 x PWRDNX 0 1 1 1 1 1 1 x SLFRSH 1 0 0 0 0 1 0 x CBR 1 1 0 0 0 1 x x MRS 1 x 0 0 0 0 0 OP code ACT 1 x 0 0 1 1 x bank row READ 1 x 0 1 0 1 0 bank col 0 col WRITE 1 x 0 1 0 0 mask bank col 0 col PALL PRE All 1 x 0 0 1 0 x x x 1 x Bank bank 0 NOP 1 x 1 x x x x x 0 1 1 1 Table 6 12 SDRAM Mo...

Page 211: ...P tRP bank row col 0 1 2 3 tRP 2 clks tRAS 2 clks tRCD 2 clks CL 2 clks 0000 0ns 50ns 100ns 150ns 200ns SDCLK nSDCS MA 24 0 nSDRAS nSDCAS nWE DATA DQM 3 0 CL CL tRCD tRCD tRP CL tRP CL tRCD tRCD row col 0 1 2 3 0000 tRP 2 clks tRAS 7 clks tRCD 2 clks CL 2 clks bank0 row 1 2 3 4 col 0ns 25ns 50ns 75ns 100ns 125ns SDCLK nSDCS MA 24 0 nSDRAS nSDCAS nWE DATA DQM 3 0 ...

Page 212: ... tRP CL CL tRCD tRAS tRCD row col 0 1 2 3 0000 tRP 2 clks tRAS 7 clks tRCD 2 clks CL 2 clks bank row 4 5 6 7 col 0000 0ns 50ns 100ns 150ns SDCLK nSDCS MA 24 0 nSDRAS nSDCAS nWE DATA DQM 3 0 CL CL CL CL tRCD tRCD tRP tRP bank row col 0 1 2 3 0000 tRP 2 clks tRAS 5 clks tRCD 2 clks CL 2 clks col 4 5 6 7 0ns 50ns 100ns SDCLK nSDCS MA 24 0 nSDRAS nSDCAS nWE DATA DQM 3 0 ...

Page 213: ...mask1 mask3 mask2 tRP 2 clks tRCD 2 clks tRAS 2 clks CL 2 clks 0ns 25ns 50ns 75ns SDCLK nSDCS MA 24 0 nSDRAS nSDCAS nWE DATA DQM 3 0 read 0 pre 1 act 1 nop write 1 nop 0 1 1 col bank row col rd0_0 rd0_1 rd0_2 rd0_3 wd1_0 wd1_1 wd1_2 wd1_3 0000 mask0 mask1 mask2 mask3 DTC 00 CL 2 tRP 1 clk tRCD 1 clk mask data bytes SDCLK 1 SDCKE 1 command nSDCS nSDRAS nSDCAS MA 24 10 nWE MD 31 0 DQM 3 0 RDnWR ...

Page 214: ...ENx the corresponding half words of MSC0 see Section 6 7 3 and MSC1 except the data width in MSCx RBWx are ignored 6 6 1 Synchronous Static Memory Configuration Register SXCNFG SXCNFG controls all synchronous static memory SXCNFG 15 0 configures chip select signals 0 and 1 SXCNFG 31 16 configures chip select signals 2 and 3 This is a read write register Ignore reads from reserved bits Write zeros ...

Page 215: ...ee Section 6 5 4 29 28 SXTP2 SX Memory type for partition pair 2 3 00 Synchronous Mask ROM SMROM 01 reserved 10 non SDRAM like Synchronous Flash 11 reserved 27 26 SXCA2 SX Memory column address bit count for partition pair 2 3 00 7 column address bits 01 8 column address bits 10 9 column address bits 11 10 column address bits 25 24 SXRA2 SX Memory row address bit count for partition pair 2 3 00 12...

Page 216: ...s for SX Memory Partition 2 bit 16 and Partition 3 bit 17 0 Partition is not Enabled as SX Memory 1 Partition is Enabled as SX Memory 15 reserved 14 SXLATCH0 SXMEM latching scheme for pair 0 1 0 Latch return data with fixed delay on MEMCLK 1 Latch return data with return clock Must always be written with a 1 to enable the return clock SDCLK for latching data For more detail on this return data lat...

Page 217: ...tween reception of the ACT command and reception of the READ command The unit size for SXRL0 is the external SDCLK cycle IF SXTP0 00 SMROM 000 1 clock 001 2 clocks 010 3 clocks 011 4 clocks 100 5 clocks 101 6 clocks 110 7 clocks 111 8 clocks IF SXTP0 10 non SDRAM timing Fast Flash this field is not used and must be programmed to 111 Table 6 13 SXCNFG Bit Definitions Sheet 3 of 4 0x4800_001C SXCNFG...

Page 218: ...which CAS Latency to use the next larger must be used IF SXTP0 00 SMROM 000 reserved 001 reserved 010 3 clocks 011 4 clocks 100 5 clocks 101 6 clocks 110 reserved 111 reserved IF SXTP0 10 non SDRAM timing Fast Flash 000 reserved 001 reserved 010 3 clocks 011 4 clocks 100 5 clocks 101 6 clocks 110 7 clocks 111 reserved 1 0 SXEN0 Enable Bits for SX Memory Partition 0 bit 0 and Partition 1 bit 1 0 Pa...

Page 219: ...n the SXCNFG CL and Table 6 15 Synchronous Static Memory External to Internal Address Mapping Options Bits Bank x Row x Col x Data External Address pins at SXMEM RAS Time MA 24 10 External Address pins at SXMEM CAS Time MA 24 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 2x12x7x32 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 21 0 8 7 6 5 4 3 2 2x12x7x1...

Page 220: ...ory Timing Diagrams Figure 6 12 shows a three beat read cycle for SMROM Table 6 16 SXMRS Bit Definitions 0x4800_0024 SXMRS Memory Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SXMRS2 reserved SXMRS0 Reset 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 Bits Name Description 31 reserved 30 16 SXMRS2 MRS value to be writ...

Page 221: ...ble 6 17 is provided only as a reference The frequency configuration must be determined based on the CLK to output delay the CLK period and the nADV to output delay timing parameters of the Flash device The values for this part number are shown as an example For Intel part number 28F800F3 programming values for this register to ensure proper operation with the processors are shown in Table 6 17 So...

Page 222: ...sh device is ignored by the processor 9 DATA OUTPUT CONFIGURATION 0 Hold data for one clock 10 reserved 0 13 11 FREQUENCY CONFIGURATION 010 CAS Latency 3 011 CAS Latency 4 100 CAS Latency 5 101 CAS Latency 6 110 CAS Latency 7 Chosen based on the AC Characteristics Read only Operation section of the Flash device data sheet 14 reserved 0 15 READ MODE 0 Synchronous Operation 1 Asynchronous Operation ...

Page 223: ...Code 2 MEMCLKs 133 66 1 5 6 6 7 147 Not supported 166 Not supported Table 6 18 Frequency Code Configuration Values Based on Clock Speed Sheet 2 of 2 MEMCLK Frequency SDCLK0 Frequency MDREFR K0DB2 Valid Frequency Configurations Corresponding CAS Latencies Figure 6 13 Burst of Eight Synchronous Flash Timing Diagram non divide by 2 mode byte address 0000 SXCNFG CL This diagram is for SXCNFG CL 100 CA...

Page 224: ...required logic GPIO_a is an unused GPIO that is driven low by software during the initialization sequence and left high during normal operation After this is completed then enable GPIO reset If Watchdog reset is not necessary a secondary GPIO can control nRESET_OUT using the equation RST nRESET nRESET_OUT GPIO_a This allows sleep mode entry to reset the flash memory while keeping it in synchronous...

Page 225: ...he VLIO transfers The use of the signals nOE nWE and nPWE is summarized below nOE is asserted for all reads nWE is asserted for Flash and SRAM writes nPWE is asserted for Variable Latency I O writes For SRAM and Variable Latency I O implementations DQM 3 0 signals are used for the write byte enables where DQM 3 corresponds to the MSB The processor supplies 26 bits of byte address for access of up ...

Page 226: ...ress pins MA 1 0 for 32 bit external bus and MA 0 for 16 bit external bus to zero and discards the unwanted portion of data When the SA 1111 compatibility bit is set for a static memory partition then two things will happen First on reads for asynchronous memory the lower address bits will correctly reflect the starting byte address This is MA 0 for 16 bit external memory and MA 1 0 for 32 bit ext...

Page 227: ... Reserved SA1111_5 SA1111_4 SA1111_3 SA1111_2 SA1111_1 SA1111_0 Reset 0 0 0 0 0 0 Bits Access Name Description 31 6 Reserved Writes must set this field to zero and Read values should be ignored 5 R W SA1111_5 Enables SA 1111 Compatibility Mode for Static Memory Partition 5 4 R W SA1111_4 Enables SA 1111 Compatibility Mode for Static Memory Partition 4 3 R W SA1111_3 Enables SA 1111 Compatibility M...

Page 228: ...e in an MSC register ensure that the new value has been accepted and programmed before issuing a command to that memory To do this the MSC register must be read after it is written and before an access to the memory is attempted This is especially important when changing from ROM Flash to an unconstrained writable memory type such as SRAM If any of the nCS 3 0 banks is configured for Synchronous S...

Page 229: ... bus Once a transaction begins on the memory bus it must be completed before another transaction starts When Synchronous Static memory devices have been enabled for a given bank this value will default to Streaming behavior assuming a faster device The register bit will still read as 0 Return Data Buffer unless it has specifically been programmed to a 1 This cannot be overridden 0 Slower device Re...

Page 230: ...mclks for Variable Latency I O nCS 5 0 For Variable Latency I O RDFx must be greater than or equal to 3 3 R W RBWx ROM bus width 0 32 bits 1 16 bits For reset value for RBW0 see Section 6 8 This value must be programmed with all memory types including Synchronous Static Memory This value must not change during normal operation Table 6 24 MSC0 1 2 Bit Definitions Sheet 2 of 3 0x4800_0008 0x4800_000...

Page 231: ...urst of four device only the lower two non byte address bits can change for burst timing For 32 bit devices this is MA 3 2 The address order can go 00 01 10 11 where the reads from 01 10 and 11 take less time to come out of the device For burst of eight devices the lower three non byte address bits can change Writes to these devices are non burst Table 6 24 MSC0 1 2 Bit Definitions Sheet 3 of 3 0x...

Page 232: ...urer For hardware reset initialization values refer to Section 6 8 MSC0 15 0 is selected when the address space corresponding to nCS0 is accessed The processor supports a ROM burst size of 1 4 or 8 by configuring the MSCx RTx register bits to 0 2 or 3 respectfully Table 6 25 Asynchronous Static Memory and Variable Latency I O Capabilities MSCx RTx Device Type Timing Memory Clocks Burst Read Addres...

Page 233: ...RDN 1 MSC0 RRR 1 0 1 2 3 4 5 6 7 00 0000 tDOH tDSOH tCEH tCES RRR 2 1 RDF 1 RDN 1 RDF 2 RDN 1 RDF 2 tAS tAS Address Setup to nCS asserted 1 clk_mem tCES nCS setup to nOE asserted 0 ns tCEH nCS hold from nOE deasserted 0 ns tDSOH MD setup to Address changing 1 5 clk_mems plus board routing delays tDOH MD hold from Address changing 0 ns MSC0 RDF0 4 RDN0 1 RRR0 1 0ns 50ns 100ns 150ns 200ns 250ns CLK_...

Page 234: ...RRR 2 1 RDF 1 RDN 1 RDF 2 RDN 1 RDF 2 tAS tAS Address Setup to nCS asserted 1 clk_mem tCES nCS setup to nOE asserted 0 ns tCEH nCS hold from nOE deasserted 0 ns tDSOH MD setup to Address changing 1 5 clk_mems plus board routing delays tDOH MD hold from Address changing 0 ns MSC0 RDF0 4 RDN0 1 RRR0 1 0ns 50ns 100ns 150ns 200ns 250ns CLK_MEM nCS 0 MA 25 5 MA 4 2 MA 1 0 nADV nSDCAS nOE nWE RDnWR MD 3...

Page 235: ...ntrols the nWE low time during a write cycle MSCx RRR is the time from nCS deassertion after a memory access to the start of another memory access MSCx RTx must be configured to 0b001 to select SRAM 6 7 5 1 SRAM Timing Diagrams and Parameters As shown in Figure 6 17 SRAM reads have the same timing as non burst ROMs except DQM 3 0 are used as byte selects For all reads DQM 3 0 are 0b0000 During wri...

Page 236: ... MEMCLK tCES nCS setup to nWE 2 MEMCLKs tASW Address setup to nWE low asserted 1 MEMCLK tDSWH Write data setup DQM to nWE high deasserted RDN 2 4 MEMCLKs tDH Data DQM hold after nWE high deasserted 1 MEMCLK tCEH nCS held asserted after nWE deasserted 1 MEMCLK tAH Address hold after nWE deasserted 1 MEMCLK nWE high time between burst beats 2 MEMCLKs Figure 6 20 32 Bit SRAM Write Timing Diagram 4 be...

Page 237: ...ssertion time for either nOE or nPWE RDF 1 Data will be latched on the rising edge of MEMCLK once the internal RDY signal is high and the minimum assertion time of RDF 1 has been reached Once the data has been latched the address may change on the next rising edge of MEMCLK or any cycles thereafter The nOE or nPWE signal will de assert one MEMCLK after data is latched Before a subsequent data beat...

Page 238: ...DN 2 RDF 1 Waits RDN RDF 1 Waits RDN RDF 1 Waits RDN 2 tAS tAS Address Setup to nCS asserted 1 clk_mem tAH Address Hold from nOE deasserted 1 clk_mem tASRW0 Address Setup to nOE asserted 1st access 3 clk_mems tASRWn Address Setup to nOE asserted next access s RDN clk_mems tCES nCS setup to nOE asserted 2 clk_mems tCEH nCS hold from nOE deasserted 1 clk_mem tDSOH MD setup to Address changing 1 5 cl...

Page 239: ...Ks tDHW Data DQM hold after nPWE high deasserted 1 MEMCLK tDHR Data hold required after nOE deasserted 0 ns tCEH nCS held asserted after nOE or nPWE deasserted 1 MEMCLK tAH Address hold after nOE or nPWE deasserted 1 MEMCLK nOE or nPWE high time between burst beats RDN 2 MEMCLKs Figure 6 22 32 Bit Variable Latency I O Write Timing Burst of Four Variable Wait Cycles Per Beat 0 1 2 3 byte addr byte ...

Page 240: ...ds to Flash before the read The Memory controller does not insert any commands before Flash reads Writes to Flash memory have the following requirements Flash memory space must be uncacheable and unbuffered Burst writes to Flash are not supported Writes to Flash must be exactly the width of the populated Flash devices on the data bus and must be a burst length of one write for example no byte writ...

Page 241: ...nous 32 Bit Flash Write Timing Diagram 2 Writes command address data address 0 0 CMD DATA 00 00 tDH tDSWH tDH tDSWH RDF 1 tAH tCEH RDF 1 tCES tASW RDF 1 tAH tCEH RDF 1 tCES tASW tAS tAS RRR 2 1 RRR 2 1 tAS Address Setup to nCS asserted 1 clk_mem tAH Address Hold from nWE deasserted 2 clk_mem tASW Address Setup to nWE asserted 3 clk_mem tCES nCS setup to nWE asserted 2 clk_mems tCEH nCS hold from n...

Page 242: ...rs Also refer to Table 6 29 Refer to Figure 6 29 and Figure 6 30 for a 16 bit PC Card Compact Flash timing diagram These are read write registers Ignore reads from reserved bits Write zeros to reserved bits These are read write registers Ignore reads from reserved bits Write zeros to reserved bits Table 6 26 MCMEM0 1 Bit Definitions 0x4800_0028 0x4800_002C MCMEM0 MCMEM1 Memory Controller Bit 31 30...

Page 243: ...s code and its affects on the command assertion 6 0 MCATTx_SE T Minimum Number of memory clocks to set up address before command assertion for MCATT for socket x is equal to MCATTx_SET 2 Table 6 28 MCIO0 1 Bit Definitions 0x4800_0038 0x4800_003C MCIO0 MCIO1 Memory Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IOx_HOLD reserved IOx_ASS...

Page 244: ...sertion time Code Code Code 2 2 Code 3 2 Code 4 3 Code 5 3 Code 6 00000 0 2 3 4 5 6 00001 1 3 5 6 8 9 00010 2 4 7 8 11 12 00011 3 5 9 10 14 15 00100 4 6 11 12 17 18 00101 5 7 13 14 20 21 00110 6 8 15 16 23 24 00111 7 9 17 18 26 27 01000 8 10 19 20 29 30 01001 9 11 21 22 32 33 01010 10 12 23 24 35 36 01011 11 13 25 26 38 39 01100 12 14 27 28 41 42 01101 13 15 29 30 44 45 01110 14 16 31 32 47 48 011...

Page 245: ...ace Command Assertion Code Table MCMEMx_ASST MCATTx_ASST MCIOx_ASST x_ASST_WAIT x_ASST_HOLD x_ASST_WAIT x_ASST_HOLD nPIOW asserted nPIOR asserted nPIOW asserted nPIOR asserted Programmed Bit Value Code decimal value MEMCLKs minimum to wait before checking for nPWAIT 1 MEMCLKs minimum to assert command nPIOW after nPWAIT 1 MEMCLKs minimum to assert command nPIOR after nPWAIT 1 MEMCLKs minimum comma...

Page 246: ...th the address signals for common memory and attribute memory accesses For I O accesses their value depends on the value of nIOIS16 and is valid a fixed amount of time after nIOIS16 is valid Common memory and attribute memory accesses assert the nPOE or nPWE control signals I O accesses assert the nIOR or nIOW control signals and use the nIOIS16 input signal to determine the bus width of the trans...

Page 247: ...important Even Byte 1 0 1 1 0 Unimportant Odd Byte Table 6 32 Common Memory Space Read Commands nPCE2 nPCE1 MA 0 nPOE nPWE MD 15 8 MD 7 0 0 0 0 0 1 Odd Byte Even Byte Table 6 33 Attribute Memory Space Write Commands nPCE2 nPCE1 MA 0 nPOE nPWE MD 15 8 MD 7 0 0 0 0 1 0 Unimportant Even Byte 1 0 0 1 0 Unimportant Even Byte 1 0 1 1 0 Unimportant Unimportant Table 6 34 Attribute Memory Space Read Comma...

Page 248: ... of these features is not required then some of the logic shown in the following diagrams can be eliminated Software is responsible for setting the MECR NOS and MECR CIT bits NOS indicates the number of sockets that the system support while CIT is written when the Card is in place Input pins nPWAIT and nIOIS16 are three stated until card detect CD signal is asserted To achieve this software progra...

Page 249: ...e enable for the low byte lane and nPCE2 controls the enable for the high byte lane Figure 6 27 Expansion Card External Logic for a One Socket Configuration MD 15 0 D 15 0 nOE DIR nCD 1 nCD 2 RDY nBSY A 25 0 nREG nCE 2 1 nOE nWE nIOR nIOW nWAIT nIOIS16 GPIO w GPIO x MA 25 0 nPREG nPOE nPWE nPIOR nPIOW nPWAIT nIOIS16 nPCE 2 1 GPIO y PSKTSEL RD nWR GPIO z Intel PXA255 Processor Socket 0 nPCD0 nPCD1 ...

Page 250: ...tion D 15 0 GPIO w GPIO x GPIO y GPIO z PSKTSEL MA 25 0 nPREG nPWAIT nPIOIS16 nPCE 1 2 nPOE nPWE nPIOW nPIOR PXA255 Processor D 15 0 CD1 CD2 RDY BSY WAIT WAIT IOIS1616 A 25 0 REG CE 1 2 OE WE IOR IOW Socket 0 D 15 0 Socket 1 DIR nPCEx nPCEx nPOE nPIOR OE DIR OE RDY BSY CD1 CD2 A 25 0 REG CE 1 2 OE WE IOR IOW IOIS1616 WAIT 6 6 6 WAIT ...

Page 251: ... MCMEM0 and MCMEM1 registers are used depending on whether card socket 0 or 1 is addressed MCIO0 and MCIO1 are used for I O accesses and MCATT0 and MCATT1 are used for access to attribute memory Figure 6 29 16 Bit PC Card Memory or I O 16 Bit Half word Access x_ASST_HOLD x_ASST_WAIT wait states x_HOLD x_SET 0ns 50ns 100ns 150ns MEMCLK MA nPREG PSKTSEL nPCE2 nPCE1 nPWE nPOE nPIOW nPIOR RDnWR nIOIS1...

Page 252: ...ed for a fixed amount of time x_ASST_HOLD 6 9 Companion Chip Interface The processor can be connected to a companion chip in two different ways Alternate Bus Master Mode Variable Latency I O See Section 6 7 6 The connection methods are illustrated in Figure 6 31 and Figure 6 32 Figure 6 30 16 Bit PC Card I O 16 Bit Access to 8 Bit Device Low Byte High Byte IOx_ASST_HOLD IOx_ASST_WAIT wait states I...

Page 253: ...le Latency IO Processor EXTERNAL SYSTEM MBREQ MBGNT GPIO 13 MBGNT GPIO 14 MBREQ nSDCS 0 nWE nSDRAS nSDCAS MD 31 0 MA 25 0 SDCLK 1 DQM 3 0 SDCKE 1 Memory Controlle External SDRAM Bank 0 Companion Chip GPIO Block Processor EXTERNAL SYSTEM nCS 0 1 2 3 4 5 nPWE nOE RDY MD 31 0 MA 25 0 DQM 3 0 Companion Chip Memory Controller ...

Page 254: ...ts SDCKE 1 at time t 5 The processor three states SDRAM outputs at time t 1 MEMCLK 6 The processor asserts MBGNT at time t 2 MEMCLKS 7 The Alternate master drives SDRAM outputs before time t 3 MEMCLKS 8 The processor asserts SDCKE 1 at time t 4 MEMCLKS During the three state period both MBREQ and MBGNT remain high and an external device can take control of the three stated pins The external device...

Page 255: ...can occur immediately after the GPIO reset assertion 6 9 1 2 nVDD_FAULT nBATT_FAULT with PMCR IDAE Disabled If an nVDD_FAULT or nBATT_FAULT occurs the processor places the GPIOs into their sleep states MBGNT must be programmed to go low during sleep The memory controller prevents the processor from entering sleep until all outstanding transactions have completed This includes waiting for the MBREQ...

Page 256: ...are determined by the three BOOT_SEL 2 0 pins and are described in Table 6 39 A description of the effect of these input pins on the Configuration registers at boot time is included in Section 6 8 6 10 2 Boot Time Defaults The following sections provide information on boot time default parameters 6 10 2 1 BOOT_DEF Read Only Register BOOT_DEF BOOT_DEF shown in Table 6 40 contains the boot up values...

Page 257: ...0 0 0 0 0 0 Bits Name Description 31 4 reserved 3 PKG_TYPE PROCESSOR TYPE read only 0 Reserved 1 PXA255 processor 2 0 BOOT_SEL BOOT SELECT read only Contains the three inputs pins BOOT_SEL 2 0 for the processor See Table 6 39 See Table 6 41 for valid boot configurations See Section 6 10 2 2 for descriptions of Boot Time Configurations Table 6 41 Valid Boot Configurations Based on Processor Type Pr...

Page 258: ...egisters are affected at reset MSC0 RBW0 MDREFR E0PIN K0RUN and SXCNFG Figure 6 33 Asynchronous Boot Time Configurations and Register Defaults BOOT_SEL 2 0 000 Asynchronous 32 bit ROM 32 MSC0 SXCNFG 0x7FF0_7FF0 0x0004_0004 RBW0 0 BOOT_SEL 2 0 001 Asynchronous 16 bit ROM 16 MSC0 SXCNFG 0x7FF0_7FF8 0x0004_0004 RBW0 1 MDREFR 0x03CA_4FFF E0PIN 0 K0RUN 0 MDREFR 0x03CA_4FFF E0PIN 0 K0RUN 0 BOOT_SEL 2 0 ...

Page 259: ...C0 SXCNFG 7FF0 7FF8 0004 4931 SXEN0 1h SXCL0 4h CL 5 SXRL0 1h RL 2 SXRA0 1h 13 bits SXCA0 2h 9 bits SXTP0 0h SXLATCH 1h RBW0 1 MRS value must be 0061h The number of banks in the device defaults to zero The number of banks in the device defaults to zero MDREFR 03CA 7FFF E0PIN 1 K0RUN 1 MDREFR 03CA 7FFF E0PIN 1 K0RUN 1 64 Mbit nWORD 1 or SMROM 16 bit 32 Mbit nWORD 0 SMROM 16 bit 32 Mbit nWORD 0 16 1...

Page 260: ...3 bits SXCA0 2h 9 bits SXTP0 0h SXLATCH 1h RBW0 0 MRS value must be 0061h BOOT_SEL 2 0 111 The number of banks in the device defaults to zero MDREFR 03CA 7FFF E0PIN 1 K0RUN 1 SMROM 16 bit 64 Mbit nWORD 0 SMROM 16 bit 64 Mbit nWORD 0 16 16 32 MSC0 SXCNFG 7FF0 7FF8 0004 4531 SXEN0 1h SXCL0 4h CL 5 SXRL0 1h RL 2 SXRA0 1h 13 bits SXCA0 1h 8 bits SXTP0 0h SXLATCH 1h RBW0 1 MRS value must be 0061h The n...

Page 261: ...following writes are allowed a Write MSC0 MSC1 MSC2 b Write MECR MCMEM0 MCMEM1 MCATT0 MCATT1 MCIO0 MCIO1 c Write MDREFR K0RUN and MDREFR E0PIN Configure MDREFR K0DB2 Retain the current values of MDREFR APD and MDREFR SLFRSH MDREFR DRI must contain a valid value Deassert MDREFR KxFREE 2 In systems that contain Synchronous Static memory write to the SXCNFG to configure all appropriate bits including...

Page 262: ...set to 0 5 For systems that contain SDRAM wait a specified NOP power up waiting period required by the SDRAMs to ensure the SDRAMs receive a stable clock with a NOP condition 6 Ensure the Data Cache bit DCACHE is disabled If this bit is enabled the refreshes triggered by the next step may not pass through to the Memory Controller properly 7 On a hardware reset in systems that contain SDRAM trigger...

Page 263: ...IO reset occurs again After all the SDRAM rows have been refreshed enable GPIO reset 6 13 Memory Controller Register Summary Table 6 43 shows the registers associated with the memory interface and the physical addresses used to access them These registers must be mapped as non cacheable and non bufferable and can only be a single word access They are grouped together in one page and all have the s...

Page 264: ...Configuration 0x4800_0040 MDMRS MRS value to be written to SDRAM 0x4800_0044 BOOT_DEF Read Only Boot time register Contains BOOT_SEL and PKG_SEL values 0x4800 0058 MDMRSLP Low Power SDRAM Mode Register Set Configuration Register Table 6 43 Memory Controller Register Summary Sheet 2 of 2 Physical Address Symbol Register Name ...

Page 265: ...tly to the LCD controller s Frame Rate Control logic When active color 16 bit pixel mode is enabled the pixel value bypasses the palette and the Frame Rate Control logic and is sent directly to the LCD controller s data pins Optionally the palette RAM is loaded for each frame by the LCD controller s DMAC Once the encoded pixel value is used to select a palette entry the value programmed within the...

Page 266: ...lor Mode 16 bits bypasses palette passive 8 bit color single panel displays passive 8 bit per panel color dual panel displays Display sizes up to 1024x1024 pixels recommended maximum of 640x480 Internal color palette RAM 256 entry by 16 bits can be loaded automatically at the beginning of each frame Encoded pixel data of 1 2 4 8 or 16 bits Programmable toggle of AC bias pin output toggled by line ...

Page 267: ...roller Figure 7 1 LCD Controller Block Diagram LCD DMA Controller Registers Palette RAM Output FIFOs Serializer To Pins From Clock Module LCDClk Pixel Data Register Data Input FIFOs TMED Dithering Engine L_DD 15 0 System Bus Control signals Configuration Encoded pixel data Raw pixel data Raw pixel data Raw pixel data Raw pixel data Dithered pixels ...

Page 268: ... monochrome displays each pin value represents a single pixel For passive color groupings of three pin values represent one pixel red green and blue subpixel data values In single panel monochrome mode L_DD 3 0 pins are used For double pixel data single panel monochrome dual panel monochrome single panel color and active color modes L_DD 7 0 are used L_DD 15 8 When dual panel color or TFT active c...

Page 269: ...t down immediately setting the quick disable bit LCSR QD This method is intended for situations such as a battery fault where system bus traffic has to be minimized immediately so the processor can have enough time to store critical data to memory before the loss of power The LCD controller must not be re enabled until the QD bit is set indicating that the quick shutdown is complete Once disabled ...

Page 270: ...ntrol The algorithm determines whether a pixel is on or off Understanding how the TMED dithering algorithm works is not necessary to use the processor LCD controller However certain characteristics of the algorithm can be controlled through the use of the TMEDRGB Seed Register Table 7 14 and the TMED Control Register TCR Table 7 15 If these registers are to be modified from their default values re...

Page 271: ...rwise the following occurs 1 The new CV is sent through the Color Offset Adjuster where it is used as a lookup into the matrix selected by TCR COAM 2 Either the 8 bit output of the chosen matrix or 00h as selected by TCR COAE is added to the appropriate color s seed register value in register TRGBR to form an offset 3 This offset is added to the result of the multiplication of the Frame Number and...

Page 272: ...y modes Programming options include wait state insertion at the beginning and end of each line and frame pixel clock L_PCLK line clock frame clock L_FCLK output enable signal polarity and frame clock pulse width See Section 7 5 for pin timing diagrams When the LCD controller is disabled all of its pins can be used for GPIO See Chapter 4 System Integration Unit for further details See also Table 7 ...

Page 273: ...display Additional pixel clocks are inserted at the end of the line to drain the remaining valid pixels from the output FIFO before HSYNC is asserted This mechanism allows an underrun to corrupt only a single line rather than an entire frame 7 3 5 3 Pixel Data Pins L_DDx Pixel data is removed from the bottom of the output FIFO and driven in parallel onto the LCD data lines on the edge of the pixel...

Page 274: ...controller is allowed to use without negatively affecting all other functions that the processor must perform 7 4 1 External Palette Buffer The external palette buffer is an off chip memory area containing up to 256 16 bit entries to be loaded into the internal palette RAM The palette buffer data does not have to be at the beginning of the external frame buffer it can also be in a separate memory ...

Page 275: ...lette RAM is bypassed Figure 7 6 1 Bit Per Pixel Data Memory Organization Figure 7 5 Palette Buffer Format Individual Palette Entry Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Color Red R Green G Blue B Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mono unused Monochrome M Little Endian Palette Entry Ordering 4 16 or 256 Entry Palette Buffer Bit 31 16 15 0 Base 0x0 Palette entry 1 Palette entry 0 Base 0...

Page 276: ... 14 Pixel 13 Pixel 3 Pixel 2 Pixel 1 Pixel 0 Base 0x4 Pixel 31 Pixel 30 Pixel 29 Pixel 19 Pixel18 Pixel 17 Pixel 16 Bit 3 2 1 0 4 bits pixel Palette Buffer Index 3 0 Bit 31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 Base 0x0 Pixel 7 Pixel 6 Pixel 5 Pixel 4 Pixel 3 Pixel 2 Pixel 1 Pixel 0 Base 0x4 Pixel 15 Pixel 14 Pixel 13 Pixel 12 Pixel 11 Pixel 10 Pixel 9 Pixel 8 Bit 7 6 5 4 3 2 1 0 8 bits pixel Pa...

Page 277: ...display to have pixels in multiples of 32 pixels for 1 bit pixels 16 pixels for 2 bit pixels 8 pixels for 4 bit pixels 4 pixels for 8 bit pixels and 2 pixels for 16 bit pixels If the LCD screen does not naturally have the correct multiple of pixels per line the user must adjust the start address for each line by adding dummy pixel values to the end of the previous line Note There are two special c...

Page 278: ... Controller can be calculated using the following equations FrameBufferSize is the result of the previous equation Bandwidth is always an important part of any system analysis Systems with large panels and high bits per pixel must ensure that the panel is not starved for data Sample calculations for an 640x480 panel 16 bits per pixel 60 Hz refresh rate FrameBufferSize 16 640 480 8 614 400 bytes Bu...

Page 279: ... Width 1 BLW Beginning of Line Pixel Clock Wait Count 1 ELW End of Line Pixel Clock Wait Count 1 L_FCLK L_LCLK L_PCLK LDD 3 0 ENB set to 1 PCP 1 VSP 0 HSP 0 Line 239 Data Line 0 Data PPL 319 BLW 0 BLW 0 ELW 0 ELW 0 VSW 2 VSW 2 HSW 1 HSW 1 ENB LCD Enable 0 LCD is disabled 1 LCD is enabled VSP Vertical Sync Polarity 0 Frame clock is active high inactive low 1 Frame clock is active low inactive high ...

Page 280: ...LCD is enabled VSP Vertical Sync Polarity 0 Vertical sync clock is active high inactive low 1 Vertical sync clock is active low inactive high HSP Horizontal Sync Polarity 0 Horizontal sync clock is active high inactive low 1 Horizontal sync clock is active low inactive high PCP Pixel Clock Polarity 0 Pixels sampled from data pins on rising edge of clock 1 Pixels sampled from data pins on falling e...

Page 281: ...he control pins Set the pulse width of the line and frame clocks pixel clock and ac bias pin frequency Set the AC bias pin toggles per interrupt Set the number of wait states to insert before and after each line and after each frame Enable various interrupt masks An additional control field exists to tune the DMAC s performance based on the type of memory system with which the processor is used Th...

Page 282: ...y blocks the generation of the interrupt request Output FIFO underruns are more critical than Input FIFO underruns since Output FIFO underruns will affect the display Branch Mask BM used to mask interrupt requests that are asserted after the LCD Controller has branched to a new set of frame descriptors See Section 7 6 6 for details Palette DMA Request Delay PDD used to select the minimum number of...

Page 283: ...d 4 pixel values each pixel clock transition When DPD 1 L_DD 7 0 pins are used to send 8 pixel values each pixel clock See Table 7 3 for a comparison of how the LCD s data pins are used in each of its display modes Note DPD does not affect dual panel monochrome mode any of the color modes or active mode Clear DPD in these modes Passive Active Display Select PAS selects whether the LCD controller o...

Page 284: ...a input pins and tie the panel s most significant data pins either high or low 3 Sometimes better results can be obtained by replicating the upper bits on the lower bits End of Frame Mask EFM used to mask interrupt requests that are asserted at the end of each frame when the DMA length of transfer counter decrements to zero When EFM 0 the interrupt is enabled and whenever the EOF status bit in the...

Page 285: ...by the LCD screen When SDS 0 single panel operation is selected pixels presented to screen a line at a time When SDS 1 dual panel operation is selected pixels presented to screen two lines at a time Single panel LCD drivers have one line row shifter and driver for pixels and one line pointer Dual panel LCD controller drivers have two line row shifters one for the top half of the screen one for the...

Page 286: ...sive Monochrome Single Panel Double Pixel Display Pixel Ordering LDD 7 LDD 6 LDD 0 LDD 7 LDD 1 LDD 0 LDD 7 Top Left Corner of Screen Column 0 Column 0 Column 2 Column 2 Column 4 Column 5 Column 5 Row 0 Row 1 Row n 2 Row n 2 1 LDD 7 LDD 6 LDD 0 LDD 7 LDD 1 LDD 0 LDD 7 LDD 15 LDD 14 LDD 8 LDD 15 LDD 9 LDD 8 LDD 15 LDD 15 LDD 14 LDD 8 LDD 15 LDD 9 LDD 8 LDD 15 LDD 7 LDD 6 LDD 5 LDD 4 LDD 3 LDD 2 LDD ...

Page 287: ...ndicating the quick disable is complete Quick disable is for sleep shutdown Regular shutdown of the LCD controller at the end of the frame can be done via the LCD Disable bit LCCR0 DIS There are separate maskable interrupts for quick disable and regular disable See Section 7 2 1 for more information This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 7 ...

Page 288: ...rors generate an interrupt 1 FIFO underrun errors do not generate an interrupt 4 SFM Start of Frame Mask 0 Starting a new frame after loading frame descriptor generates an interrupt 1 Start of frame SOF condition does not generate an interrupt 3 LDM LCD Disable Done Mask 0 LCD disable done condition generates an interrupt state of LDD status sent to the interrupt controller 1 LCD disable done cond...

Page 289: ...xel clock frequency When the counter reaches zero L_LCLK is negated HSW can be programmed to generate a line clock pulse width ranging from 1 to 64 pixel clock periods The pixel clock does not toggle during the line clock pulse in passive display mode but does toggle in active display mode The polarity active and inactive state of the line clock pin is programmed using the horizontal sync polarity...

Page 290: ...count the number of line clock periods to wait After the count has elapsed the VSYNC L_FCLK signal is pulsed EFW generates a wait period ranging from 0 to 255 line clock cycles EFW 0x00 disables the EOF wait count L_LCLK does not toggle during the generation of the EFW line clock periods Table 7 4 LCCR1 Bit Definitions Physical Address 0x4400_0004 LCD Controller Control Register 1 LCD Controller B...

Page 291: ...ive mode VSW must be programmed to allow enough wait states to occur between frames such that the LCD s DMAC is able to fully load the on chip palette if applicable a sufficient number of encoded pixel values to be fetched from the frame buffer to be processed by the dither logic and placed in the output FIFO ready to be sent to the LCD data pins The number of wait states required is system depend...

Page 292: ... 0 0 0 Bits Name Description 31 24 BFW Beginning of frame line clock wait count In active mode LCCR0 PAS 1 value 0 255 specifies the number of line clock periods to add to the beginning of a frame before the first set of pixels is sent to the display The Line clock does toggle during the insertion of the extra line clock periods BFW must be cleared to zero disabled in passive mode 23 16 EFW End of...

Page 293: ...ain forced to its inactive state Vertical Sync Polarity VSP selects the active and inactive states of the L_FCLK pin When VSP 0 L_FCLK is active high and inactive low When VSP 1 L_FCLK is active low and inactive high In active display mode LCCR0 PAS 1 L_FCLK serves as the vertical sync signal It is forced to its inactive state while pixels are transmitted during the frame After the end of the fram...

Page 294: ... displays which can result in more time between line clocks than expected See Section 7 3 5 for more information on how output FIFO underruns are handled In active display mode the ACB bit field has no effect on the L_BIAS pin Because the pixel clock toggles continuously in active mode the AC bias pin is used as an output enable signal It is asserted automatically by the LCD controller in active m...

Page 295: ...el 4 entry 8 byte palette buffer only first 2 entries are used 001 2 bits pixel 4 entry 8 byte palette buffer 010 4 bits pixel 16 entry 32 byte palette buffer 011 8 bits pixel 256 entry 512 byte palette buffer 100 16 bits pixel no palette buffer 101 110 111 reserved 23 OEP Output Enable Polarity 0 L_BIAS pin is active high and inactive low in active display mode 1 L_BIAS pin is active low and inac...

Page 296: ...undary in main memory word 0 contains the value for FDADRx 19 16 API AC bias Pin transitions per Interrupt Value 0 15 is used to specify the number of AC bias pin transitions to count before setting the line count status ABC bit signalling an interrupt request The counter is frozen when ABC is set and is restarted when ABC is cleared by software This function is disabled when API 0x0 15 8 ACB AC B...

Page 297: ...in this register are undefined The target address must be aligned to a 16 byte boundary Bits 2 0 of the address must be zero These are read write registers Ignore reads from reserved bits Write zeros to reserved bits 7 6 5 3 LCD DMA Frame Source Address Registers FSADRx FSADR0 and FSADR1 shown in Table 7 8 correspond to DMA channels 0 and 1 and contain the source address of the current descriptor ...

Page 298: ...re read only registers Ignore reads from reserved bits Table 7 8 FSADRx Bit Definitions Physical Address channel 0 0x4400_0204 channel 1 0x4400_0214 FSADR0 FSADR1 LCD Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Frame Source Address Reset Bits Name Description 31 0 Frame Source Address Address of the palette or pixel frame data in memory Bits...

Page 299: ...ed from memory and before the palette frame data is fetched In dual panel mode LCSR SOF is set only when both channels reach the start of frame and both frame descriptors have SOFINT set SOFINT must not be set for palette descriptors in dual panel mode since only one channel is ever used to load the palette RAM End Of Frame Interrupt EOFINT when set the DMAC sets the end of frame bit LCSR EOF afte...

Page 300: ...PAL must not be set in LDCMD1 25 23 reserved 22 SOFINT Start of Frame Interrupt 0 Do not set the SOF interrupt bit in the LCD status register when starting a new frame 1 Set the start of frame SOF interrupt bit in the LCD status register when starting a new frame after loading the frame descriptor 21 EOFINT End of Frame Interrupt 0 Do not set the EOF interrupt bit in the LCD status register when f...

Page 301: ...ers Ignore reads from reserved bits Write zeros to reserved bits Table 7 11 FBRx Bit Definitions Physical Address channel 0 0x4400_0020 channel 1 0x4400_0024 LCD DMA Frame Branch Registers LCD Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Frame Branch Address reserved BINT BRA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X 0...

Page 302: ... controller has branched and loaded the descriptor from the frame branch address in the frame branch register and the branch interrupt BINT bit in the frame branch register is set When BS is set an interrupt request is made to the interrupt controller if it is unmasked LCCR0 BM 0 In dual panel mode LCCR0 SDS 1 both DMA channels are enabled and BS is set only after both channels frames have been fe...

Page 303: ...lue in API but does not start to decrement again until ABC is cleared by software Bus Error Status BER set when a DMA transfer causes a system bus error The error is signalled when the DMA controller attempts to access a reserved or nonexistent memory space When this occurs the DMA controller stops and remains halted until software installs a valid memory address into the FDADRx register In dual c...

Page 304: ...hed fetching a frame with the EOFINT bit set in its descriptor 7 QD LCD Quick Disable status maskable interrupt 0 LCD has not been quickly disabled by clearing LCCCR0 ENB 1 LCD has been quickly disabled 6 OU Output FIFO Underrun status maskable interrupt 0 Output FIFOs have not underrun 1 LCD dither logic is not supplying data to output FIFOs for the panel at a sufficient rate The output FIFOs hav...

Page 305: ...us error status nonmaskable interrupt 0 DMA has not attempted an access to reserved nonexistent memory space 1 DMA has attempted an access to a reserved nonexistent location in external memory 1 SOF Start Of Frame status maskable interrupt 0 A new frame descriptor with its SOFINT bit set has not been fetched 1 The DMA has begun fetching a new frame with its SOFINT bit set 0 LDD LCD Disable Done st...

Page 306: ...ocess for passive DSTN displays The default recommended setting is 0x00AA5500 This setting provides superior display results in most cases This is a write only register Write zeros to reserved bits Table 7 14 TRGBR Bit Definitions Physical Address 0x4400_0040 TMED RGB Seed Register LCD Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBS...

Page 307: ...n 7 3 3 TMED Vertical Beat Suppression TVBS is the block shift value used as an offset that is combined with the pixel counter TMED Frame Number Adjuster Enable FNAME allows the frame number adjuster to add an offset to the current frame number before the value is sent through the algorithm Setting this bit enables the addition of the current frame number to a value composed from the row and colum...

Page 308: ...ntal Beat Suppression Specifies the column shift value 7 4 TVBS TMED Vertical Beat Suppression Specifies the block shift value 3 FNAME TMED Frame Number Adjuster Enable 0 Disable frame number adjuster 1 Enable frame number adjuster 2 COAE TMED Color Offset Adjuster Enable 0 Disable color offset adjuster 1 Enable color offset adjuster 1 FNAM TMED Frame Number Adjuster Matrix 0 Selects Matrix 1 for ...

Page 309: ...A channel 0 frame descriptor address register 0x4400_0204 FSADR0 DMA channel 0 frame source address register 0x4400_0208 FIDR0 DMA channel 0 frame ID register 0x4400_020C LDCMD0 DMA channel 0 command register 0x4400_0210 FDADR1 DMA channel 1 frame descriptor address register 0x4400_0214 FSADR1 DMA channel 1 frame source address register 0x4400_0218 FIDR1 DMA channel 1 frame ID register 0x4400_021C...

Page 310: ...7 46 Intel PXA255 Processor Developer s Manual LCD Controller ...

Page 311: ...wide transmit and receive data FIFOs The FIFOs may be loaded or emptied by the Central Processor Unit CPU using programmed I O or DMA burst transfers of 4 or 8 half words per transfer while receiving or transmitting 8 2 Signal Description This section describes the SSPC signals 8 2 1 External Interface to Synchronous Serial Peripherals Table 8 1 lists the external signals that connect the SSP to a...

Page 312: ... of a programmed I O or a DMA burst with 4 or 8 half words being transferred per burst The SSPC then takes the data from the FIFO serializes it and transmits it via the SSPTXD signal to the peripheral Data from the peripheral is received via the SSPRXD signal converted to parallel words and is stored in the Receive FIFO Read operations automatically target the receive FIFO while write operations w...

Page 313: ...th requested data one clock after the last bit of the requesting message Return data part of the same frame can be from 4 to 16 bits in length Total frame length is 13 to 33 bits The serial clock SSPSCLK only toggles during an active frame At other times it is held in an inactive or idle state as defined by its specified protocol 8 4 1 1 SSP Format Details When outgoing data in the SSP controller ...

Page 314: ...e configured SSPSCLK edge and is sampled by the controller on opposite edge At the end of the frame SSPSFRM is deasserted high one clock period after the last bit is latched at its destination and the completed incoming word is shifted into the incoming FIFO The peripheral can tristate SSPRXD after sending the last bit of the frame SSPTXD retains the last value transmitted when the controller goes...

Page 315: ...es to toggle at the bit rate One bit period after the last command bit the peripheral must return the serial data requested most significant bit first on SSPRXD Data transitions on SSPSCLK s falling edge and is sampled on the rising edge SSPSCLK s last falling edge coincides with the end of the last data bit on SSPRXD and it remains low if it is the only or last word of the transfer SSPSFRM deasse...

Page 316: ...16 bit field the stored data sample is right justified the word s least significant bit is stored in bit 0 and unused bits are packed as zeroes above the most significant bit Logic in the SSPC automatically left justifies data in the Transmit FIFO so the sample is properly transmitted on SSPTXD in the selected frame format Figure 8 3 National Microwire Frame Format SSPSCLK SSPSFRM SSPTXD Bit 7 Bit...

Page 317: ...ontroller can also be programmed to transfer data to and from the SSP s FIFO s Refer to Chapter 5 DMA Controller for instructions on programming the DMA channels The steps for the DMA programming model are 1 Program the transmit receive byte count buffer length and burst size 2 Program the DMA request to channel map register for SSP 3 Set the run bit in the DMA control register 4 Set the desired v...

Page 318: ...s of the 32 bit word A read cycle or burst read similarly transfers data from the receive FIFO The FIFOs are independent buffers that allow full duplex operation The SSPC Status Register SSSR indicates the state of the FIFO buffers whether the programmable threshold has been passed and whether a transmit or receive FIFO service request is active It also shows how many entries are occupied in the F...

Page 319: ... 0 0 Bits Name Description 3 0 DSS Data Size Select 0000 reserved undefined operation 0001 reserved undefined operation 0010 reserved undefined operation 0011 4 bit data 0100 5 bit data 0101 6 bit data 0110 7 bit data 0111 8 bit data 1000 9 bit data 1001 10 bit data 1010 11 bit data 1011 12 bit data 1100 13 bit data 1101 14 bit data 1110 15 bit data 1111 16 bit data 5 4 FRF Frame Format 00 Motorol...

Page 320: ...ff chip clock is used the user must set the appropriate bits in the GPIO alternate function and pin direction registers that correspond to the pin See Chapter 4 System Integration Unit for more details on configuring GPIO pins for alternate functions Note Disable the SSPC by setting the SSPC Enable SSE to a 0 before setting the ECS bit to a 1 The ECS bit may be set to one either before the SSE is ...

Page 321: ...l SSP functions Table 8 3 SSCR1 Bit Definitions Sheet 1 of 2 0x4100_0004 SSP Control Register 1 SSCR1 Synchronous Serial Port Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RFT TFT MWDS SPH SPO LBM TIE RIE Reset X 0x0 0x0 0 0 0 0 0 0 Bits Name Description 0 RIE Receive FIFO Interrupt Enable 0 Receive FIFO interrupt is disabled 1 Receiv...

Page 322: ...ade to the interrupt controller If the TIE bit is set to a 0 neither the TFS bit s current state nor the transmit FIFO logic s ability to set and clear the TFS bit is affected However the interrupt request generation is blocked The TIE bit s state does not affect the transmit FIFO DMA request generation that is asserted when the TFS bit is set to a 1 8 7 2 3 Loop Back Mode LBM The loop back mode L...

Page 323: ...of an SSPSCLK period before SSPSFRM is deasserted high at the end of the frame When SPH 1 SSPSCLK remains in its inactive idle state as determined by the SPO setting for one half cycle after SSPSFRM is asserted low at the beginning of a frame SSPSCLK continues to transition for the rest of the frame and is then held in its inactive state for one full SSPSCLK period before SSPSFRM is deasserted hig...

Page 324: ...r to Table 8 4 for suggested TFT values associated with DMA servicing 8 7 2 8 Receive FIFO Interrupt DMA Threshold RFT This 4 bit value sets the level at or above which the FIFO controller triggers a DMA service interrupt and if enabled an interrupt request Refer to Table 8 4 for suggested RFT values associated with DMA servicing Be careful not to set the RFT value too high for your system or the ...

Page 325: ...efore it is written to the SSDR Transmit logic left justifies the data and ignores any unused bits Received data less than 16 bits is automatically right justified in the receive FIFO When the SSPC is programmed for National Microwire frame format and the size for transmit data is 8 bits as selected by the MWDS bit in the SSCR1 the most significant byte is ignored SSCR0 DSS controls receive data s...

Page 326: ...nterrupt generated Bits that cause an interrupt will signal the request as long as the bit is set When the bit is cleared the interrupt is cleared Read write bits are called status bits read only bits are called flags Status bits are referred to as sticky once set by hardware they must be cleared by software Writing a 1 to a sticky status bit clears it Writing a 0 has no effect Read only flags are...

Page 327: ...y 1 Receive FIFO is not empty 4 BSY SSP Busy read only 0 SSP is idle or disabled 1 SSP currently transmitting or receiving a frame 5 TFS Transmit FIFO Service Request read only 0 Transmit FIFO level exceeds TFT threshold or SSP disabled 1 Transmit FIFO level is at or below TFT threshold generate interrupt or DMA request 6 RFS Receive FIFO Service Request read only 0 Receive FIFO level exceeds RFT ...

Page 328: ... TIE bit After the CPU or the DMA fills the FIFO such that it exceeds the threshold the TFS flag and the service request and or interrupt is automatically cleared 8 7 4 5 Receive FIFO Service Request Flag RFS This bit contains a maskable interrupt and is set when the receive FIFO is nearly filled and requires service to prevent an overrun RFS is set any time the receive FIFO has the same or more v...

Page 329: ... Write zeros to reserved bits 8 8 SSP Controller Register Summary Table 8 7 shows the SSP registers associated with the SSP controller and their physical addresses Table 8 7 SSP Controller Register Summary Address Abbreviation Full Name 0x4100_0000 SSCR0 SSP Control Register 0 0x4100_0004 SSCR1 SSP Control Register 1 0x4100_0008 SSSR SSP Status Register 0x4100_000C reserved 0x4100_0010 SSDR Write ...

Page 330: ...8 20 Intel PXA255 Processor Developer s Manual Synchronous Serial Port Controller ...

Page 331: ...e that resides on the processor internal bus Data is transmitted to and received from the I2 C bus via a buffered interface Control and status information is relayed through a set of memory mapped registers Refer to The I2 C Bus Specification for complete details on I2C bus operation Note The I2 C unit does not support the hardware general call 10 bit addressing or CBUS compatibility 9 2 Signal De...

Page 332: ...es to drive the bus lines and to communicate status about events such as arbitration wait states error conditions etc For example when a master drives the clock SCL line during a data transfer it transfers a bit on every instance that the clock is high When the slave is unable to accept or drive data at the rate that the master is requesting the slave can hold the clock line low between the high s...

Page 333: ... the I2 C Status Register ISR are located in the I2 C memory mapped address space The registers and their functions are defined in Section 9 9 The I2 C unit supports a fast mode operation of 400 Kbits sec and a standard mode of 100 Kbits sec Refer to The I2 C Bus Specification for details 9 3 2 I2 C Bus Interface Modes The I2 C unit can accomplish a transfer in different operation modes Table 9 3 ...

Page 334: ...and a transaction STOP bus state used at the end of a transfer A START condition occurs if a high to low transition takes place on the SDA line when SCL is high A STOP condition occurs if a low to high transition takes place on the SDA line when SCL is high The I2 C unit uses the ICR START and ICR STOP bits to Initiate an additional byte transfer Initiate a START condition on the I2C bus Enable Da...

Page 335: ... STOP Condition The no START or STOP condition ICR START 0 ICR STOP 0 is used in master transmit mode while the I2 C unit is transmitting multiple data bytes see Figure 9 2 Software writes the data byte and the I2 C unit sets the ISR ITE bit and clears the ICR TB bit The software then writes a new byte to the IDBR and sets the ICR TB bit which initiates the new byte transmission This process conti...

Page 336: ...ssor Developer s Manual I2 C Bus Interface Unit Figure 9 3 START and STOP Conditions Data byte ACK NAK ACK NAK R nW START Target Slave Address ACK NAK Data Byte STOP No START or STOP Condition START Condition STOP Condition ...

Page 337: ...t passes the information to the serial bus when the ICR TB bit is set See Section 9 9 3 When the I2C unit is in master or slave transmit mode 1 Software writes data to the IDBR over the internal bus This initiates a master transaction or sends the next data byte after the ISR ITE bit is set 2 I2 C unit transmits data from the IDBR when the ICR TB bit is set 3 When enabled an IDBR transmit empty in...

Page 338: ...I2 C unit aborts the transaction by automatically sending a STOP and setting the ISR BED bit When the I2 C unit is enabled and idle it remains in slave receive mode and monitors the I2 C bus for a START signal When it detects a START pulse the I2 C unit reads the first seven bits and compares them to those in the ISAR and the general call address 0x00 When the bits match those in the ISAR register...

Page 339: ...ress independent of the value in the ICR ACKNAK bit In slave receive mode an ACK response automatically follows a data byte independent of the value in the ICR ACKNAK bit The I2 C unit sends the ACK value after it receives the eighth data bit in a byte In slave transmit mode the I2 C unit receives a NAK from the master to indicate the last byte has been transferred The master then sends a STOP or ...

Page 340: ...leted its period The master with the longest low period holds down the SCL line Masters with shorter periods are held in a high wait state until the master with the longest period completes After the master with the longest period completes the SCL line changes to the high state and masters with the shorter periods continue the data cycle 9 4 5 2 SDA Arbitration Arbitration on the SDA line can con...

Page 341: ...s in case an arbitration process is interrupted by a repeated START or STOP condition transmitted on the I2 C bus To prevent errors the I2 C unit acts as a master if no arbitration takes place in the following circumstances Between a repeated START condition and a data bit Between a data bit and a STOP condition Between a repeated START condition and a STOP condition These situations occur if diff...

Page 342: ...t Master receive CPU writes to least significant IDBR bit with target slave address If low master remains a master transmitter If high master transitions to a master receiver See Section 9 4 2 Signal START Condition Master transmit Master receive See Generate clock output above Performed after target slave address and R nW bit are in IDBR Software sets ICR START bit Software sets ICR TB bit to ini...

Page 343: ... IDBR Receive Full Interrupt is enabled it is signalled to the CPU When the IDBR is read if the ISR ACKNAK is clear indicating ACK the processor writes the ICR ACKNAK bit and set the ICR TB bit to initiate the next byte read If the ISR ACKNAK bit is set indicating NAK ICR TB bit is clear ICR STOP bit is set and ISR UB bit is set then the last data byte has been read into the IDBR and the I2 C unit...

Page 344: ...ave Receiver Figure 9 10 A Complete Data Transfer Master to Slave Slave to Master START Slave Address R nW 1 ACK Data Byte ACK Data Byte STOP N Bytes ACK ACK Default Slave Receive Mode First Byte Read START Slave R nW 1 ACK Data Byte ACK Data Byte N Bytes ACK Read ACK Sr Slave R nW 0 ACK Data Byte ACK Data Byte STOP N Bytes ACK Write ACK Address Address Master to Slave Slave to Master Repeated Sta...

Page 345: ...d if enabled after the matching slave address is received and acknowledged Read one byte of I2 C Data from the IDBR Slave receive only Data receive mode of I2C slave operation Eight bits are read from the serial bus into the shift register When a full byte is received and the ACK NAK bit is completed the byte is transferred from the shift register to the IDBR Occurs when the ISR IRF bit is set and...

Page 346: ...ction The least significant bit of the second byte called B defines the transaction Table 9 7 shows the valid values and definitions when B 0 Figure 9 11 Master Transmitter Write to Slave Receiver Figure 9 12 Master Receiver Read to Slave Transmitter Figure 9 13 Master Receiver Read to Slave Transmitter Repeated START Master Transmitter Write to Slave Receiver Master to Slave Slave to Master START...

Page 347: ...cted to reset the I2 C unit except for ISAR returns to the default reset condition ISAR is not affected by a reset When B 1 the sequence is a hardware general call and is not supported by the I2 C unit Refer to the The I2 C Bus Specification for information on hardware general calls I2C 10 bit addresses and CBUS compatibility are not supported Figure 9 14 General Call Address Table 9 7 General Cal...

Page 348: ...ad data byte to transfer in the IDBR 8 Set the ICR TB bit 9 Write a 1 to the ISR ITE bit to clear interrupt 10 Return from interrupt 11 Repeat steps 6 to 10 for n 1 times If at any time the slave does not have data the I2C unit keeps SCL low until data is available 12 When a IDBR Transmit Empty interrupt occurs Read ISR IDBR Transmit Empty 1 ACK NAK 1 R nW bit 0 13 Write a 1 to the ISR ITE bit to ...

Page 349: ...ss Detected interrupt 3 Set the ICR IUE and ICR SCLE bits to enable the I2C unit and SCL 9 6 2 Write 1 Byte as a Master 1 Load target slave address and R nW bit in the IDBR R nW must be 0 for a write 2 Initiate the write Set ICR START clear ICR STOP clear ICR ALDIE set ICR TB 3 When an IDBR Transmit Empty interrupt occurs Read ISR IDBR Transmit Empty 1 Unit Busy 1 R nW bit 0 4 Write a 1 to the ISR...

Page 350: ...ite 2 Initiate the write Set ICR START clear ICR STOP clear ICR ALDIE set ICR TB 3 When an IDBR Transmit Empty interrupt occurs Read ISR IDBR Transmit Empty 1 Unit Busy 1 R nW bit 0 4 Write a 1 to the ISR ITE bit to clear interrupt 5 Load data byte to be transferred in the IDBR 6 Initiate the write Clear ICR START clear ICR STOP set ICR ALDIE set ICR TB 7 When an IDBR Transmit Empty interrupt occu...

Page 351: ...P and ICR ACKNAK bits 10 Initiate the read Clear ICR START clear ICR STOP set ICR ALDIE set ICR ACKNAK set ICR TB ICR STOP is not set because STOP or repeated start will be decided on the byte read 11 When an IDBR Receive full interrupt occurs Read ISR IDBR Receive Full 1 Unit Busy 1 R nW bit 1 ACK NAK bit 1 12 Write a 1 to the ISR IRF bit to clear the interrupt 13 Read IDBR data 14 Initiate STOP ...

Page 352: ...the IDBR over the internal bus The processor writes data to the IDBR when a master transaction is initiated or when the IDBR Transmit Empty Interrupt is signalled Data moves from the IDBR to the shift register when the Transfer Byte bit is set The IDBR Transmit Empty Interrupt is signalled if enabled when a byte is transferred on the I2 C bus and the acknowledge cycle is complete If the IDBR is no...

Page 353: ... 31 8 reserved 7 0 IDB I2 C Data Buffer Buffer for I2 C bus send receive data Table 9 10 ICR Bit Definitions Sheet 1 of 3 Physical Address 4030_1690 I2 C Control Register I2 C Bus Interface Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FM UR SADIE ALDIE SSDIE BEIE IRFIE ITEIE GCD IUE SCLE MA TB ACKNAK STOP START Reset 0 0 0 0 0 0 0 0 0 0 0 ...

Page 354: ... SCL line 1 Enables the I2C clock output for master mode operation 4 MA Master Abort generates a STOP without transmitting another data byte when the I2 C unit is in master mode 0 The I2 C unit transmits STOP using the STOP ICR bit only 1 The I2 C unit sends STOP without data transmission In master transmit mode after a data byte is sent the ICR s Transfer Byte bit is cleared and IDBR Transmit Emp...

Page 355: ...gative ACK NAK after it receives a data byte The I2 C unit automatically sends an ACK pulse when it responds to its slave address or when it responds in slave receive mode independent of the ACK NAK control bit setting 1 STOP STOP initiates a STOP condition after the next data byte on the I2C bus is transferred in master mode In master receive mode the ACK NAK control bit must be set along with th...

Page 356: ...ear this bit write a 1 to it 8 GCAD General Call Address Detected 0 No general call address received 1 I2 C unit received a general call address 7 IRF IDBR Receive Full 0 The IDBR has not received a new data byte or the I2 C unit is idle 1 The IDBR register received a new data byte from the I2 C bus An interrupt is signalled when the IRFIE is set to a 1 To clear this bit write a 1 to it 6 ITE IDBR...

Page 357: ...ine when the transferred byte is the last one Updated after each byte and ACK NAK information is received 0 RWM Read Write Mode 0 I2 C unit is in master transmit or slave receive mode 1 I2 C unit is in master receive or slave transmit mode R nW bit of the slave address Automatically cleared by hardware after a stop state Table 9 11 ISR Bit Definitions Sheet 2 of 2 Physical Address 4030_1698 I2C St...

Page 358: ...9 28 Intel PXA255 Processor Developer s Manual I2 C Bus Interface Unit ...

Page 359: ...ammable baud rate generator that allows the internal clock to be divided by 1 to 216 1 to generate an internal 16X clock Modem control pins that allow flow control through software Each UART has different modem control capability Fully programmable serial interface 5 6 7 or 8 bit characters Even odd and no parity detection 1 1 5 or 2 stop bit generation Baud rate generation up to 921 Kbps for the ...

Page 360: ...itter and receiver logic Software can program interrupts to meet its requirements This minimizes the number of computations required to handle the communications link Each UART operates in an environment that is controlled by software and can be polled or is interrupt driven 10 2 1 Full Function UART The FFUART supports modem control capability The maximum tested baud rate on this UART is 230 4 kb...

Page 361: ...TS input has changed state since the last time the Modem Status Register was read nCTS has no effect on the transmitter This signal is present on the FFUART and BTUART When the CTS bit of the MSR changes state and the Modem Status interrupt is enabled an interrupt is generated nDSR Input DATA SET READY When low indicates that the modem or data set is ready to establish a communications link with a...

Page 362: ...I signal Bit 2 the trailing edge of ring indicator TERI of the MSR indicates whether the nRI input signal has changed from low to high since the MSR was last read This signal is only present on the FFUART When the RI bit of the MSR changes from a high to low state and the Modem Status interrupt is enabled an interrupt is generated nDTR Output DATA TERMINAL READY When low signals the modem or the d...

Page 363: ...ceiver waits for a frame start bit and the transmitter sends data if it is available in the Transmit Holding Register Transmit data can be written to the Transmit Holding Register before the UART unit is enabled In FIFO mode data is transmitted from the FIFO to the Transmit Holding Register before it goes to the pin When the UART unit is disabled the transmitter or receiver finishes the current by...

Page 364: ... Value Register Accessed Base 0 Receive Buffer read only Base 0 Transmit Buffer write only Base 0x04 0 Interrupt Enable read write Base 0x08 X Interrupt Identification read only Base 0x08 X FIFO Control write only Base 0x0C X Line Control read write Base 0x10 X Modem Control read write Base 0x14 X Line Status read only Base 0x18 X Modem Status read only Base 0x1C X Scratch Pad read write Base 0x20...

Page 365: ...le 10 6 store the divisor in a 16 bit binary format Load these divisor latches during initialization to ensure that the baud rate generator operates properly If each Divisor Latch is loaded with a 0 the 16X clock stops The Divisor Latches are accessed with a word write The baud rate of the data shifted in to or out of a UART is given by the formula For example if the divisor is 24 the baud rate is...

Page 366: ...ked Receiver Line Status interrupts occur when the error is at the front of the FIFO Note When DMA requests are enabled and an interrupt occurs software must first read the LSR to see if an error interrupt exists then check the IIR for the source of the interrupt When the last error byte is read from the FIFO DMA requests are automatically enabled Software is not required to check for the error in...

Page 367: ...MIE RLSE TIE RAVIE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 8 reserved 7 DMAE DMA Requests Enable 0 DMA requests are disabled 1 DMA requests are enabled 6 UUE UART Unit Enable 0 The unit is disabled 1 The unit is enabled 5 NRZE NRZ coding Enable NRZ encoding decoding is only used in UART mode not in infrared mode If the slow infrared receiver o...

Page 368: ...upt is deasserted This is a read only register Ignore reads from reserved bits Table 10 8 Interrupt Conditions Priority Level Interrupt origin 1 highest Receiver Line Status one or more error bits were set 2 Received Data is available In FIFO mode trigger level was reached In non FIFO mode RBR has data 2 Character Timeout Indication occurred Occurs only in FIFO mode when data is in the receive FIF...

Page 369: ...rupt SET RESET Function 3 2 1 0 Priority Type Source Cleared By 0 0 0 1 None No interrupt is pending 0 1 1 0 Highest Receiver Line Status Overrun error parity error framing error break interrupt Reading the LSR 0 1 0 0 Second Highest Received Data Available Non FIFO mode Receive buffer is full FIFO mode Trigger level was reached Non FIFO mode Reading the Receiver Buffer Register FIFO mode Reading ...

Page 370: ...er FIFO 0 0 0 0 Fourth Highest Modem Status Clear to Send Data Set Ready Ring Indicator Data Carrier Detect Reading the Modem Status Register Table 10 10 Interrupt Identification Register Decode Sheet 2 of 2 Interrupt ID Bits Interrupt SET RESET Function Table 10 11 FCR Bit Definitions Sheet 1 of 2 Base 0x08 FIFO Control Register UART Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 371: ...e cleared The DR bit in the LSR is reset to 0 All the error bits in the FIFO and the FIFOE bit in the LSR are cleared Any error bits OE PE FE or BI that had been set in LSR are still set The receiver shift register is not cleared If the IIR had been set to Received Data Available it is cleared 0 Writing 0 has no effect 1 The receiver FIFO is cleared 0 TRFIFOE Transmit and Receive FIFO Enable TRFIF...

Page 372: ...logic In FIFO mode wait until the transmitter is idle LSR TEMT 1 to set and clear SB 0 no effect on TXD output 1 forces TXD output to 0 space 5 STKYP Sticky Parity Forces the bit value at the parity bit location to be the opposite of the EPS bit rather than the parity value This stops parity generation If PEN 0 STKYP is ignored 0 no effect on parity bit 1 forces parity bit to be opposite of EPS bi...

Page 373: ...9 8 7 6 5 4 3 2 1 0 reserved FIFOE TEMT TDRQ BI FE PE OE DR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Bits Name Description 31 8 reserved 7 FIFOE FIFO Error Status In non FIFO mode this bit is 0 In FIFO Mode FIFOE is set to 1 when there is at least one parity error framing error or break indication for any of the characters in the FIFO A processor read to the LSR does n...

Page 374: ...its The Break indicator is reset when the processor reads the LSR In FIFO mode only one character equal to 0x00 is loaded into the FIFO regardless of the length of the break condition BI shows the break condition for the character at the front of the FIFO not the most recently received character 0 No break signal has been received 1 Break signal received 3 FE Framing Error FE indicates that the re...

Page 375: ... and the most recently received byte has been discarded The OE indicator is set upon detection of an overrun condition and cleared when the processor reads the LSR 0 No data has been lost 1 Received data has been lost 0 DR Data Ready Set when a complete incoming character has been received and transferred into the Receive Buffer Register or the FIFO In non FIFO mode DR is cleared when the receive ...

Page 376: ... input The four modem control inputs nCTS nDSR nDCD and nRI are disconnected from the pins and the modem control output pins nRTS and nDTR are forced to their inactive state Coming out of the loopback mode may result in unpredictable activation of the delta bits bits 3 0 in the Modem Status Register It is recommended that MSR is read once to clear the delta bits in the MSR Loopback mode must be co...

Page 377: ...preserved If the UART is re enabled transmission will continue where it stopped Interrupts from the flow control pins will not come through the UART unit if the unit is disabled When disabling the unit because of flow control interrupts must be enabled in the processor Interrupt Controller for the flow control pins The Interrupt Controller will still trigger interrupts if the pins are in Alternate...

Page 378: ...nt to MCR OUT1 if MCR LOOP is set 0 nRI pin is 1 1 nRI pin is 0 5 DSR Data Set Ready Complement of the Data Set Ready nDSR input Equivalent to MCR DTR if MCR LOOP is set 0 nDSR pin is 1 1 nDSR pin is 0 4 CTS Clear To Send Complement of the Clear to Send nCTS input Equivalent to MCR RTS if MCR LOOP is set 0 nCTS pin is 1 1 nCTS pin is 0 3 DDCD Delta Data Carrier Detect 0 No change in nDCD pin since...

Page 379: ...received data available interrupt IIR 0xC4 is lower The line status interrupt occurs only when the character at the front of the FIFO has errors The data ready bit DR in the LSR is set when a character is transferred from the shift register to the Receive FIFO The DR bit is cleared when the FIFO is empty 10 4 3 2 Character Timeout Indication Interrupt A character timeout indication interrupt occur...

Page 380: ...FIFO mode The transmit DMA request is generated when the transmit FIFO is at least half empty and IER DMAE is set After the transmit DMA request is generated the DMA Controller DMAC writes data to the FIFO For each DMA request the DMAC sends 8 16 or 32 bytes of data to the FIFO The number of bytes to be transmitted is programmed in the DMA channel The receive DMA request is generated when the rece...

Page 381: ...us Interface The Slow Infrared SIR interface is used with the STUART to support two way wireless communication that uses infrared transmission The SIR provides a transmit encoder and receive decoder to support a physical link that conforms to the IRDA Serial Infrared Specification Version 1 1 The SIR interface does not contain the actual IR LED driver or the receiver amplifier The I O pins attache...

Page 382: ...Width Select When XMODE is cleared the UART 16X clock is used to clock the IRDA transmit and receive logic When XMODE is set the transmit encoder generates 1 6 µs pulses that are 3 16 of a bit time at 115 2 kbps instead of pulses 3 16 of a bit time wide and the receive decoder expects pulses will be 1 6µs wide also 0 Transmit pulse width is 3 16 of a bit time wide 1 Transmit pulse width is 1 6 µs ...

Page 383: ...each zero bit The shorter infrared pulse generated when XMODE is set reduces the LEDs power consumption At 2400 bps the LED is normally on for 78 µs for each zero bit that is transmitted When XMODE is set the LED is on only 1 6 µs XMode changes the behavior of the receiver The receiver expects pulses of the correct pulse width If the transceiver crops the incoming pulse then Xmode must be set Note...

Page 384: ... Holding register write only 0x4010_0004 0 FFIER IER read write 0x4010_0008 X FFIIR Interrupt ID register read only 0x4010_0008 X FFFCR FCR write only 0x4010_000C X FFLCR LCR read write 0x4010_0010 X FFMCR MCR read write 0x4010_0014 X FFLSR LSR read only 0x4010_0018 X FFMSR MSR read only 0x4010_001C X FFSPR Scratch Pad Register 0x4010_0020 X FFISR Infrared Selection register read write 0x4010_0000...

Page 385: ...R Transmit Holding register write only 0x4070_0004 0 STIER IER read write 0x4070_0008 X STIIR Interrupt ID register read only 0x4070_0008 X STFCR FCR write only 0x4070_000C X STLCR LCR read write 0x4070_0010 X STMCR MCR read write 0x4070_0014 X STLSR LSR read only 0x4070_0018 X STMSR reserved no modem control pins 0x4070_001C X STSPR Scratch Pad Register 0x4070_0020 X STISR Infrared Selection regi...

Page 386: ...ptions for BTMCR BTMSR and STMCR are modified as shown in Table 10 21 Table 10 21 Flow Control Registers in BTUART and STUART Bit7 5 Bit4 Bit3 Bit2 Bit1 Bit0 BTMCR reserved LOOP OUT2 reserved RTS reserved BTMSR reserved CTS reserved reserved reserved DCTS STMCR reserved LOOP OUT2 reserved reserved reserved ...

Page 387: ...1 1 Signal Description The FICP signals are IRRXD and IRTXD Table 11 1 describes each signal s function Most IrDA transceivers also have enable and speed pins Use GPIOs to enable the transceiver and select the speed See Chapter 4 System Integration Unit for more information 11 2 FICP Operation The FICP is disabled and does not have control of the port s pins after a reset Before software enables t...

Page 388: ... possible 2 bit combinations and Figure 11 2 shows an example of 4PPM modulation for the byte 0b10110001 which is constructed with four chips Bits within each nibble are not reordered but nibble 0 least significant is transmitted first and nibble 3 most significant is transmitted last Figure 11 1 4PPM Modulation Encodings Chip Timeslots 1 2 3 4 Data 0b00 Data 0b01 Data 0b10 Data 0b11 Figure 11 2 4...

Page 389: ...receive address The AME bit in the FICP control register 0 ICCR0 determines the address match function The received frames addresses are stored in the receive FIFO with normal data 11 2 4 Control Field The control field is an optional 8 bit field that is defined by software The FICP does not provide hardware decode support for the control byte It treats all bytes between the address and the CRC as...

Page 390: ...he receive data line To encode a 4 Mbps data stream the required chip frequency is 2 0 MHz with four timeslots per chip at a frequency of 8 0 MHz Receive data is sampled halfway through each timeslot period by counting three of the six 48 MHz clock periods that make up each timeslot see Figure 11 2 The chips are synchronized during the reception preamble The pattern of four chips repeated 16 times...

Page 391: ...ompletely filling the receive logic attempts to place additional data into the full FIFO and an overrun error is signalled When the FIFO is full all subsequent data bytes received are lost and all FIFO contents remain intact If the data field contains any invalid chips such as 0011 1010 1110 the frame aborts and the oldest byte in the temporary FIFO is moved to the receive FIFO the remaining tempo...

Page 392: ... to receive data or signal the FICP to attempt to transmit the aborted frame again At the end of each transmitted frame the FICP sends a pulse called the serial infrared interaction pulse SIP A SIP must be sent at least every 500 ms to ensure that low speed devices 115 2 Kbps and slower do not interfere with devices that transmit at higher speeds The SIP simulates a start bit that causes low speed...

Page 393: ...s in the FIFO are called trailing bytes Trailing bytes do not trigger a receive DMA request Instead they trigger the end error in FIFO ICSR0 EIF interrupt which is nonmaskable When ICSR0 EIF is set DMA requests are disabled The core must read bytes from the FIFO until ICSR0 EIF is cleared The core must also read bytes from the FIFO until ICSR0 EIF is cleared if there are errors in FIFO entries bel...

Page 394: ...on Do not put data in the receive FIFO unless address is recognized or address is the broadcast address 6 TIE Transmit FIFO interrupt enable 0 Transmit FIFO service request ICSR0 TFS does not generate an interrupt 1 Transmit FIFO service request generates an interrupt Setting TIE does not clear TFS or prevent TFS from being set or cleared by the transmit FIFO TIE does not affect transmit FIFO DMA ...

Page 395: ...smit FIFO underrun can either end the current frame normally or transmit an abort 0 Transmit FIFO underrun causes CRC stop flag and SIP to be transmitted and masks transmit underrun interrupt generation 1 Transmit FIFO underrun causes abort to be transmitted and generates an interrupt Clearing ICCR0 TUS does not affect the current state of ICSR0 TUR or prevent TUR from being set or cleared by the ...

Page 396: ...s 0x4080_0004 Fast Infrared Communication Port Control Register 1 ICCR1 Fast Infrared Communication Port Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AMV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 8 reserved 7 0 AMV Address match value The 8 bit value used by receiver logic to compare to addre...

Page 397: ...iption 31 4 reserved 3 RXP Receive pin polarity select 0 Data from the receive data pin is inverted before being used by the FICP unit 1 Data from the receive data pin to the FICP unit is not inverted Set on reset 2 TXP Transmit pin polarity select 0 Data from the FICP is inverted before being sent to the transmit data pin 1 Data from the FICP is not inverted before being sent to the transmit data...

Page 398: ...ister The end error in FIFO EIF flag is set in status register 0 when a tag bit is set in any of the receive FIFO s bottom eight 16 or 32 entries as determined by the trigger level The EIF flag is cleared when no error bits are set in the FIFO s bottom entries When EIF is set an interrupt is generated and the receive FIFO DMA request is disabled Software must empty the FIFO and check for the EOF C...

Page 399: ...rs This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 11 6 ICSR0 Bit Definitions Sheet 1 of 2 0x4080_0014 Fast Infrared Communication Port Status Register 0 ICSR0 Fast Infrared Communication Port Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FRE RFS TFS RAB TUR EIF Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 400: ... is idle 0 EIF End error in FIFO read only 0 Bits 8 10 are not set within any of the entries at or below the trigger level of the receive FIFO Receive FIFO DMA service requests are enabled 1 One or more tag bits 8 10 are set within the entries at or below the trigger level of the receive FIFO Request interrupt disable receive FIFO DMA service requests This interrupt is not maskable in the FICP Onc...

Page 401: ...ry is transferred to the ROR bit 5 CRE CRC error read only 0 CRC not encountered yet or no CRC check errors encountered in the receipt of data 1 CRC calculated on the incoming data Does not match CRC value contained within the received frame Each time an 11 bit value reaches the bottom of the receive FIFO bit 9 from the last FIFO entry is transferred to the CRE bit 4 EOF End of frame read only 0 C...

Page 402: ... and the physical addresses used to access them Table 11 8 FICP Register Summary Address Name Description 0x4080_0000 ICCR0 FICP control register 0 0x4080_0004 ICCR1 FICP control register 1 0x4080_0008 ICCR2 FICP control register 2 0x4080_000C ICDR FICP data register 0x4080_0010 reserved 0x4080_0014 ICSR0 FICP status register 0 0x4080_0018 ICSR1 FICP status register 1 ...

Page 403: ...acket types include token start of frame data and handshake Packets are assembled into groups to produce transactions Transactions fall into four groups bulk control interrupt and isochronous Endpoint 0 is used only to communicate the control transactions that configure the UDC Endpoint 0 s responsibilities include connection address assignment endpoint configuration bus enumeration and disconnect...

Page 404: ...ular endpoint the Megacell can load the same endpoint for the next frame transmission While the Megacell unloads an OUT endpoint the UDC can continue to process the next incoming packet to that endpoint 12 3 USB Protocol After a core reset or when the USB host issues a USB reset the UDC configures all endpoints and is forced to use the USB default address zero After the UDC configures the endpoint...

Page 405: ...e to the Resume state a 1 to 0 transition to signal the Start of Packet SOP Each USB packet begins with a Sync field that starts with the 1 to 0 transition see Section 12 3 1 After the packet data is transferred the bus signals the End of Packet EOP state by pulling both UDC and UDC low for 2 bit times followed by an Idle state for 1 bit time If the idle persists for more than 3 ms the UDC enters ...

Page 406: ...The PID is 1 byte wide and always follows the sync field The first four bits contain an encoded value that represents packet type Token Data Handshake and Special packet format and type of error detection The last four bits contain a check field that ensures the PID is transmitted without errors The check field is generated by performing a ones complement of the PID The UDC XORs the PID and CRC fi...

Page 407: ... 1 5 Mbps USB transmission The UDC supports high speed 12 Mbps USB transfers only PRE packets that signify low speed devices and the low speed data transfer that follows such PRE packets are ignored 12 3 4 1 Token Packet Type A Token packet is placed at the beginning of a frame and is used to identify OUT IN SOF and SETUP transactions OUT and IN frames are used to transfer data SOF packets are use...

Page 408: ...received without bit stuffing CRC or PID check errors NAK indicates that the UDC was unable to accept data from the host or has no data to transmit STALL indicates that the UDC was unable to transmit or receive data and requires host intervention to clear the stall condition The receiving unit signals Bit stuffing CRC and PID errors by omitting a handshake packet Table 12 6 shows the format of a h...

Page 409: ...ons by default use DATA0 type transfers Table 12 9 shows the four types of control transactions Table 12 7 Bulk Transaction Formats Action Token Packet Data Packet Handshake Packet Host successfully received data from UDC IN DATA0 DATA1 ACK UDC temporarily unable to transmit data IN None NAK UDC endpoint needs host intervention IN None STALL Host detected PID CRC or bit stuff error IN DATA0 DATA1 ...

Page 410: ...s interrupt transactions begin with a setup packet followed by an optional data packet then a handshake packet Interrupt transactions by default use DATA0 type transfers Figure 12 10 shows the four types of interrupt transactions 12 3 6 UDC Device Requests The UDC uses its control status and data registers to control and monitor the transmit and receive FIFOs for endpoints 1 15 The host controls a...

Page 411: ...nts of 256 bytes each the host is not be able to schedule the proper bandwidth and does not take the UDC out of Configuration 0 The user device determines which endpoints to report to the host If an endpoint is not reported it is not used Another option attractive for use with isochronous endpoints is to describe a configuration of a packet with a maximum size less than 256 bytes to the host For e...

Page 412: ... devices 12 4 1 Self Powered Device Figure 12 2 shows how to connect the USB interface for a self powered device The 0 Ω resistors are optional and if they are not used USB D must connect directly to the device UDC D and connect USB D must connect directly to the device UDC D The UDC D and UDC D pins are designed to match the impedance of a USB cable 90 Ω without external series resistors To allow...

Page 413: ...t which appears to be a disconnect to the host PC The peripheral is put in sleep mode When the peripheral comes out of sleep mode software must drive a 1 to the GPIOx pin to indicate to the host PC that a high speed USB peripheral is connected 12 4 1 2 When GPIOn and GPIOx are the Same Pin After a reset GPIOn is configured to act as an input and to cause an interrupt on a rising or falling edge Wh...

Page 414: ...buffer while UDCCS0 RNE bit receiver not empty is set 6 Software parses the command in the buffer and determines that it is a Control Read 7 Software starts to load the UDDR0 register FIFO with the first data packet and sets the internal state machine to EP0_IN_DATA_PHASE 8 After it reads and parses the data software clears the UDCCS0 SA and the UDCCS0 OPR bits and sets the UDCCS0 IPR bit if trans...

Page 415: ... the UDDR0 register FIFO with the first data packet and sets the internal state machine to EP0_IN_DATA_PHASE 8 After it reads and parses the data software clears the UDCCS0 SA and the UDCCS0 OPR bits and sets the UDCCS0 IPR bit if transmitting less than MAX_PACKET bytes which prompts the UDC to transmit the data on the next IN The UDC sends NAKs to all requests on this EP until the UDCCS0 IPR bit ...

Page 416: ...pt service routine 10 The host PC issues an OUT packet and the UDC issues an EP0 interrupt 11 Software enters the ISR routine and determines that it is in the EP0_OUT_DATA_PHASE state the UDCCS0 OPR bit is set and the UDCCS0 SA bit is clear This indicates that there is more data to receive 12 Software reads the data into a buffer while UDCCS0 RNE bit is set and clears the UDDCCS0 OPR bit 13 Softwa...

Page 417: ...A bits If the command is a No Data Phase Standard command then do not set the UDCCS0 IPR bit If the command is not a No Data Phase Standard command e g a No Data Phase Vendor command or No Data Phase Class command then software must set the UDCCS0 IPR bit 8 When the host PC executes the STATUS IN stage the UDC sends back a zero length packet which indicates a successful handshake This does not cau...

Page 418: ...EP1 data FIFO UDDR1 with data and clears the UDCCS1 TPC bit If the data packet is a short packet software also sets the UDCCS1 TSP bit 2 The host PC sends a BULK IN and the UDC sends a data packet back to the host PC and generates an EP1 Interrupt 3 Software fills the EP1 data FIFO UDDR1 with data and clears the UDCCS1 TPC bit If the data packet is a short packet software also sets the UDCCS1 TSP ...

Page 419: ...S2 RNE is set software uses the UDCWC2 count register to read the proper amount of data from the EP2 data FIFO UDDR2 5 Software clears the UDCCS2 RPC bit 6 Return from interrupt 7 Steps 2 through 6 repeat until all the data has been read from the host 12 5 7 Case 7 EP3 Data Transmit ISOCHRONOUS IN The procedure in Case 7 can also be used to operate Endpoints 8 and 13 In Case 7 the Transmit Short P...

Page 420: ... If the data packet is a short packet software also sets the UDCCS3 TSP bit 2 The host PC sends a ISOC IN command and the UDC sends a data packet back to the host PC and generates an EP3 Interrupt 3 Software fills the EP3 data FIFO UDDR3 with data and clears the UDCCS3 TPC bit If the data packet is a short packet software also sets the UDCCS3 TSP bit 4 Return from interrupt 5 Steps 2 through 4 rep...

Page 421: ...ftware sets up a descriptor to receive each data packet then reads the remaining data on each UDCCS2 RSP bit interrupt and sets up another descriptor c If the packet size is less than 32 bytes software must use interrupt mode 2 The host PC sends a ISOC OUT 3 The DMA engine reads the data from the EP4 data FIFO UDDR4 4 Steps 2 and 3 repeat until all the data has been read from the host 5 If the sof...

Page 422: ...nd 15 In Case 9 the Transmit Short Packet is only set if a packet size of less than 8 bytes is sent If the packet size is 8 bytes the system arms when the 8th byte is loaded Loading the 8th byte and setting the UDCCS5 TSP bit produces one 8 byte packet and one zero length packet When software receives a SETUP VENDOR command to set up an EP5 INTERRUPT IN transaction it can only allow the Megacell t...

Page 423: ...at a USB suspend has occurred and software takes any necessary actions to turn off other peripherals clean up internal buffers perform power management and perform similar functions Software must not disable the UDC and must not allow the processor to go into sleep mode while the USB cable is attached 12 5 12 Case 12 RESUME Interrupt 1 As software starts it clears the UDCCR SRM bit to allow a USB ...

Page 424: ...shifter are reset All entries in the transmit and receive FIFO are also reset Table 12 12 UDCCR Bit Definitions 0x 4060_0000 UDCCR Read Write and Read Only Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved REM RSTIR SRM SUSIR RESIR RSM UDA UDE x x x x x x x x x x x x x x x x x x x x x x x x 1 0 1 0 0 0 0 0 Bits Name Description 31 8 reserved 7 REM R...

Page 425: ... will not generate an interrupt but status continues to be updated 12 6 1 6 Suspend Resume Interrupt Mask SRM This bit masks or enables the suspend interrupt request to the interrupt controller When SRM is 1 the interrupt is masked and the setting of SUSIR will not generate an interrupt When SRM is 0 the setting of SUSIR generates an interrupt when the USB is idle for more than 6ms Programming SRM...

Page 426: ...nse enable AREN bit enables user control of the ACK response to the status IN requests of SET_CONFIGURATION and SET_INTERFACE commands When ACM is set to 1 the UDC responds to the STATUS IN request following a Table 12 13 UDC Control Function Register 0x 4060_0008 UDCCFR USB Device Controller Bit 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved AREN...

Page 427: ... have been written to the endpoint 0 FIFO to be transmitted The core must not set this bit if a max_packet is to be transmitted The UDC clears this bit when the packet has been successfully transmitted the Table 12 14 UDCCS0 Bit Definitions 0x 4060_0010 UDCCS0 USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SA RNE FST SST DRW...

Page 428: ...ndicates the state of the device remote wakeup feature by sending a Set Feature command or a Clear Function command The UDC decodes the command sent by the host and sets this bit to a 1 if the feature is enabled and a 0 if the feature is disabled This bit is read only 12 6 3 5 Sent Stall SST The sent stall bit is set by the UDC when FST successfully forces a software induced STALL on the USB bus T...

Page 429: ...gnified by loading 64 bytes of data or by setting UDCCSx TSP Table 12 15 UDCCS1 6 11 Bit Definitions 0x 4060_0014 0x 4060_0028 0x 4060_003C UDCCS1 UDCCS6 UDCCS11 USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TSP reserved FST SST TUR FTF TPC TFS X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 1 Bit Name Descrip...

Page 430: ...rrun When the UDC experiences an underrun NAK handshakes are sent to the host UDCCSx TUR does not generate an interrupt and is for status only UDCCSx TUR is cleared by writing a 1 to it 12 6 4 5 Sent STALL SST The sent stall bit is set by the UDC in response to FST successfully forcing a user induced STALL on the USB bus This bit is not set if the UDC detects a protocol violation from the host PC ...

Page 431: ...CCS12 USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RSP RNE FST SST DME reserved RPC RFS x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 Bit Name Description 31 8 reserved 7 RSP Receive short packet read only 1 Short packet received and ready for reading 6 RNE Receive FIFO not empty read only 0 Receive FIFO ...

Page 432: ...d of packet has been received and the receive FIFO has less than 32 bytes of data remaining in it If the bit is not set the interrupt is asserted when the end of packet is received and all of the received data is still in the receive FIFO 12 6 5 5 Sent Stall SST The sent stall bit is set by the UDC in response to FST successfully forcing a user induced STALL on the USB bus This bit is not set if t...

Page 433: ...read write registers Ignore reads from reserved bits Write zeros to reserved bits 12 6 6 UDC Endpoint x Control Status Register UDCCS3 8 13 USCCS3 8 13 shown in Table 12 17 contains 4 bits that are used to operate endpoint x an Isochronous IN endpoint Table 12 17 UDCCS3 8 13 Bit Definitions 0x4060_001C 0x4060_0030 0x4060_0044 UDCCS3 UDCCS8 UDCC13 USB Device Controller Bit 31 30 29 28 27 26 25 24 2...

Page 434: ...to load the transmit buffers the interrupt generated by UDCCSx TPC can be masked to allow data to be transmitted without core intervention 12 6 6 3 Flush Tx FIFO FTF The Flush Tx FIFO bit triggers a reset for the endpoint s transmit FIFO The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or SET_INTERFACE The bit s read value is zero 12 6 6 4 T...

Page 435: ...use neither FIFO buffer has room for them This bit is cleared by writing a 1 to it Table 12 18 UDCCS4 9 14 Bit Definitions 0x 4060_0020 0x 4060_0034 0x4060_0048 UDCCS4 UDCCS9 UDCCS14 USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RSP RNE reserved DME ROF RPC RFS Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0...

Page 436: ...acket in the active buffer currently being read is a short packet or zero sized packet This bit is updated by the UDC after the last byte is read from the active buffer and reflects the status of the new active buffer If UDCCSx RSP is a one and UDCCSx RNE is a zero it indicates a zero length packet If a zero length packet is present the core must not read the data register UDCCSx RSP clears when t...

Page 437: ...t triggers a reset for the endpoint s transmit FIFO The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or SET_INTERFACE The bit s read value is zero 5 FST Force STALL read write 1 Issue STALL handshakes to IN tokens 4 SST Sent STALL read write 1 to clear 1 STALL handshake was sent 3 TUR Transmit FIFO underrun read write 1 to clear 1 Transmit F...

Page 438: ... a STALL handshake to all IN tokens STALL handshakes continue to be sent until the core clears this bit by sending a Clear Feature command The UDCCSx SST bit is set when the STALL state is actually entered but this may be delayed if the UDC is active when the UDCCSx FST bit is set The UDCCSx FST bit is automatically cleared when the UDCCSx SST bit is set To ensure that no data is transmitted after...

Page 439: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 Reset x x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 Bits Name Description 31 8 reserved 7 IM7 Interrupt Mask for Endpoint 7 0 Receive interrupt enabled 1 Receive interrupt disabled 6 IM6 Interrupt Mask for Endpoint 6 0 Transmit interrupt enabled 1 Trans...

Page 440: ...m reserved bits Write zeros to reserved bits Table 12 21 UICR1 Bit Definitions 0x 4060_0054 UICR1 USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 Reset X X X X X X X X X X X X X X X X X X X X X X X X 1 1 1 1 1 1 1 1 Bits Name Description 31 8 reserved 7 IM15 Interrupt mask for Endpoint 15...

Page 441: ...s register the OUT packet ready bit is set the IN packet ready bit is cleared or the sent STALL bit is set The IR0 bit is cleared by writing a 1 to it 12 6 11 2 Endpoint 1 Interrupt Request IR1 The interrupt request bit is set if the IM1 bit in the UDC interrupt control register is cleared and the IN packet complete TPC in UDC endpoint 1 control status register is set The IR1 bit is cleared by wri...

Page 442: ...endpoint 4 control status register or the Isochronous Error Endpoint 4 IPE4 in the UFNHR are set The IR4 bit is cleared by writing a 1 to it 12 6 11 6 Endpoint 5 Interrupt Request IR5 The interrupt request bit is set if the IM5 bit in the UDC interrupt control register is cleared and the IN packet complete TPC in UDC endpoint 5 control status register is set The IR5 bit is cleared by writing a 1 t...

Page 443: ... complete TPC or in UDC endpoint 10 control status register is set The IR10 bit is cleared by writing a 1 to it Table 12 23 USIR1 Bit Definitions 0x 4060_005C USIR1 USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IR15 IR14 IR13 IR12 IR11 IR10 IR9 IR8 x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 Bits Name De...

Page 444: ...ansmit Underrun TUR in UDC endpoint 13 control status register is set The IR13 bit is cleared by writing a 1 to it 12 6 12 7 Endpoint 14 Interrupt Request IR14 The interrupt request bit is set if the IM14 bit in the UDC interrupt control register is cleared and the OUT packet ready RPC or receiver overflow ROF in the UDC endpoint 14 control status register or the Isochronous Error Endpoint 14 IPE1...

Page 445: ...generation of endpoint 9 To maintain synchronization software must monitor this bit when it services the SOF interrupt and reads the frame number This bit is not set if the token packet is corrupted or if the sync or PID fields of the data packet are corrupted Table 12 24 UFNHR Bit Definitions 0x 4060_0060 UFNHR USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ...

Page 446: ...t of Frame Interrupt Request SIR The interrupt request bit is set if the UFNHR SIM bit is cleared and an SOF packet is received The UFNHR SIR bit is cleared by writing a 1 to it This is a read write register Ignore reads from reserved bits Write zeros to reserved bits 12 6 14 UDC Frame Number Low Register UFNLR UFNLR shown in Table 12 25 is the eight least significant bits of the 11 bit frame numb...

Page 447: ... at specific points in a control sequence The direction that the FIFO flows is controlled by the UDC Normally the UDC is in an idle state waiting for the host to send commands When the host sends a command the UDC fills the FIFO with the command from the host and the core reads the command from the FIFO when it arrives The only time the core may write the endpoint 0 FIFO is after a valid command f...

Page 448: ... received the UDC will issue a NAK to the host the next time it sends an OUT packet to endpoint x This NAK condition will remain in place until a full packet space is available in the UDC at Endpoint x Table 12 27 UDDR0 Bit Definitions 0x 4060_0080 UDDR0 USB Device Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Bottom of Endpoint 0 FIF...

Page 449: ...oved and the packet behind it has already been received the UDC issues a NAK to the host the next time it sends an OUT packet to Endpoint x This NAK condition remains in place until a full packet space is available in the UDC at Endpoint x These are read only registers Ignore reads from reserved bits Table 12 29 UDDR2 7 12 Bit Definitions 0x 4060_0180 0x 4060_0680 0x 4060_0B80 UDDR2 UDDR7 UDDR12 U...

Page 450: ...26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved 8 bit Data Reset x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 Bits Name Description 31 8 reserved 7 0 DATA Top of endpoint data currently being loaded Table 12 32 UDDR5 10 15 Bit Definitions 0x 4060_00A0 0x 4060_00C0 0x 4060_00E0 UDDR5 UDDR10 UDDR15 USB Device Controller Bit 31 30 29 28 27 26 25 24 2...

Page 451: ...Register 0x4060_004C UDCCS15 UDC Endpoint 15 Interrupt Control Status Register 0x4060_0050 UICR0 UDC Interrupt Control Register 0 0x4060_0054 UICR1 UDC Interrupt Control Register 1 0x4060_0058 USIR0 UDC Status Interrupt Register 0 0x4060_005C USIR1 UDC Status Interrupt Register 1 0x4060_0060 UFNHR UDC Frame Number Register High 0x4060_0064 UFNLR UDC Frame Number Register Low 0x4060_0068 UBCR2 UDC ...

Page 452: ..._0B00 UDDR11 UDC Endpoint 11 Data Register 0x4060_0B80 UDDR12 UDC Endpoint 12 Data Register 0x4060_0C00 UDDR13 UDC Endpoint 13 Data Register 0x4060_0E00 UDDR14 UDC Endpoint 14 Data Register 0x4060_00E0 UDDR15 UDC Endpoint 15 Data Register Table 12 33 USB Device Controller Register Summary Sheet 3 of 3 Address Name Description ...

Page 453: ...chapter describes the programming model for the ACUNIT The information in this chapter requires an understanding of the AC 97 revision 2 0 specification Note The ACUNIT and the I2 S Controller cannot be used at the same time 13 2 Feature List The processor ACUNIT supports the following AC 97 features Independent channels for stereo Pulse Code Modulated PCM In Stereo PCM Out modem out modem in and ...

Page 454: ...Configure the other AC 97 signals as previously described b In the Global Control Register GCR Set the GCR COLD_RST bit Refer to Table 13 7 for more details Note Refer to Section 4 1 3 GPIO Register Definitions on page 4 6 for details on programing the GPDR and GAFR for use with the ACUNIT 13 3 2 Example AC link Figure 13 1 shows an example interconnect for an AC link The ACUNIT supports one or tw...

Page 455: ... or an analog to digital converter ADC both having a minimum 16 bit resolution The ACUNIT supports the data streams shown in Table 13 2 Figure 13 1 Data Transfer Through the AC link nACRESET SDATA_OUT SYNC 48 kHz SDATA_IN_0 BITCLK 12 288 MHz AC 97 Controller Unit AC 97 Primary CODEC AC 97 Secondary CODEC SDATA_IN_1 ACUNIT AC link Table 13 2 Supported Data Stream Formats Sheet 1 of 2 Channel Slots ...

Page 456: ...ificant bit LSB The Tag Phase s first bit is bit 15 and the first bit of each slot in Data Phase is bit 19 The last bit in any slot is bit 0 Figure 13 2 shows Tag and Data Phase organization for the ACUNIT and the CODEC The figure also lists the slot definitions that the ACUNIT supports 13 4 1 AC link Audio Output Frame SDATA_OUT The audio output frame data stream corresponds to the multiplexed bu...

Page 457: ...me slot the ACUNIT stuffs all trailing non valid bit positions of the 20 bit slot with zeroes For example if a 16 bit sample stream is being played to an AC 97 DAC the first 16 bit positions are presented to the DAC MSB justified They are followed by the next four bit positions that the ACUNIT stuffs with zeroes This process ensures that the least significant bits do not introduce any DC biasing r...

Page 458: ...for more details The control interface architecture supports up to sixty four16 bit read write registers addressable on even byte boundaries Only accesses to even registers 0x00 0x02 etc are valid Accesses to odd registers 0x01 0x03 etc are not valid Audio output frame slot 1 communicates control register address and write read command information to the ACUNIT Two CODECs are connected to the sing...

Page 459: ...C GPIO Pin Status read data is sent by the CODEC over the AC link in the same frame that the read request was sent to the CODEC The CODEC GPIO Pin Status read data is sent in Slot 12 of the incoming stream A CODEC with a GPIO Pin Status register must constantly send the status of the register in slot 12 13 4 1 3 Slot 2 Command Data Port Slot 2 is the Command Data Port Slot 2 in conjunction with th...

Page 460: ... sent in Slot 12 of the next outgoing frame where Slot 12 is then marked as valid 3 After the first write to address 0x54 Slot 12 remains valid for all subsequent frames The data transmitted on Slot 12 is the data last written to address 0x54 Any subsequent write to the register sends the new data out on the next frame 4 Following a system reset or AC 97 cold reset Slot 12 is invalidated Slot 12 r...

Page 461: ...s sampled on BITCLK s falling edge 13 4 2 1 Slot 0 Tag Phase In Slot 0 the first bit is a global bit SDATA_IN slot 0 bit 15 that indicates whether or not the CODEC is in the CODEC ready state If the CODEC Ready bit is a 0 the CODEC is not ready for operation This condition is normal after power is asserted on reset i e while the CODEC voltage references are settling When the AC link CODEC Ready in...

Page 462: ...ter index Slot 1 of incoming stream matches the last valid control register index that was sent in Slot 1 of the outgoing stream of the most recent previous frame For multiple sample rate output the CODEC examines its sample rate control registers its FIFOs states and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active low SLOTR...

Page 463: ...its its ADC output data MSB first and fills any trailing non valid bit positions with zeroes 13 4 2 6 Slot 5 Optional Modem Line CODEC Slot 5 contains MSB justified line modem ADC output data if the line modem CODEC is supported The ACUNIT only supports a 16 bit ADC output resolution from the optional line modem 13 4 2 7 Slot 6 Optional Dedicated Microphone Record Data Slot 6 contains an optional ...

Page 464: ...in the ACUNIT So when software initiates a read of the CODEC register at address 0x54 in the modem CODEC I O space the read data is already inside the ACUNIT 13 5 AC link Low Power Mode Software must set the ACLINK_OFF bit of the GCR to one before the processor enters Sleep Mode The ACUNIT then drives SYNC and SDATA_OUT to a logic low level The ACUNIT maintains nACRESET high when ACLINK_OFF is set...

Page 465: ...amples SYNC low before it can start BITCLK The CODEC that signaled the wake event must keep its SDATA_IN high until it detects that a warm reset has been completed The CODEC can then transition its SDATA_IN low Figure 13 8 shows the AC link timing for a wake up triggered by a CODEC Because the processor may need to be awakened the Power Management unit detects the AC 97 wake up event SDATA_IN high...

Page 466: ... driven high for a minimum of one microsecond The CODEC must not activate BITCLK until it samples SYNC low again This prevents a new audio frame from being falsely detected 13 6 ACUNIT Operation The ACUNIT can be accessed through the processor or the DMA controller The processor uses programmed I O instructions to access the ACUNIT and it can access four register types ACUNIT registers Accessible ...

Page 467: ...NIT are reset on power up After power up the nACRESET signal remains asserted until the audio or modem driver sets the COLD_RST bit of the GCR to one During operation clearing the COLD_RST bit to zero resets the ACUNIT and CODEC To initialize the ACUNIT follow theses steps 1 Program the GPIO Direction register and GPIO Alternate Function Select register to assign proper pin directions for the ACUN...

Page 468: ...13 16 Intel PXA255 Processor Developer s Manual AC 97 Controller Unit ACUNIT does not set the CODEC ready bit GCR PCRDY for the Primary CODEC or GCR SCRDY for the Secondary CODEC ...

Page 469: ... The ACUNIT sets the CDONE bit of the GSR to one after the completion of a CODEC write operation For details refer to Table 13 8 Software clears this bit by writing a 1 to it To read a CODEC the software must complete the following steps 1 Software issues a dummy read to the CODEC register The ACUNIT responds to this read operation with invalid data The ACUNIT then initiates the read access across...

Page 470: ...ntries upper 16 bits are always zero A receive FIFO triggers a DMA request when the FIFO has eight or more entries A transmit FIFO triggers a DMA request when it holds less than eight entries A transmit FIFO must be half full filled with eight entries before any data is transmitted across the AC link 13 8 1 1 Transmit FIFO Errors Channel specific status bits are updated during transmit under run c...

Page 471: ...upt Interrupts the CPU when a CODEC register s status address and data reception are completed Software writes a one to this bit to clear it Primary CODEC ready interrupt Sets a status register bit when the Primary CODEC is ready The CODEC sets bit 0 of Slot 0 on the input frame to signal that it is ready Software clears the PRIRDY_IEN bit of the GCR to clear this interrupt Secondary CODEC ready i...

Page 472: ... Write zeros to reserved bits Table 13 7 GCR Bit Definitions Sheet 1 of 2 Physical Address 4050_000C GCR Register AC 97 Controller Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CDONE_IE SDONE_IE reserved SECRDY_IEN PRIRDY_IEN reserved SECRES_IEN PRIRES_IEN ACLINK_OFF WARM_RST COLD_RST GIE Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 473: ...warm reset while BITCLK is running the write will be ignored and the bit will not change This bit is self clearing i e it remains set until the reset completes and BITCLK is seen on the AC link after which it clears itself 1 COLD_RST AC 97 Cold Reset 0 Causes a cold reset to occur throughout the AC 97 circuitry All data in the ACUNIT and the CODEC will be lost 1 A cold reset is not generated Defau...

Page 474: ...ompletions 0 The CODEC read completed normally 1 The CODEC read resulted in a timeout The bit remains set until cleared by software This bit is cleared by software writing a 1 to this location 14 BIT3SLT12 Bit 3 of slot 12 Display Bit 3 of the most recent valid slot 12 13 BIT2SLT12 Bit 2 of slot 12 Display Bit 2 of the most recent valid slot 12 12 BIT1SLT12 Bit 1 of slot 12 Display Bit 1 of the mo...

Page 475: ...e modem in channel interrupts occurred When the specific interrupt is cleared this bit will be cleared interruptible 0 GSCI CODEC GPI Status Change Interrupt GSCI 0 Bit 0 of slot 12 is clear 1 Bit 0 of slot 12 is set This indicates that one of the GPI s changed state and that the new values are available in slot 12 The bit is cleared by software writing a 1 to this bit location interruptible Table...

Page 476: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FEIE reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description Table 13 10 PICR Bit Definitions Physical Address 4050_0004 PICR Register AC 97 Controller Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FEIE ...

Page 477: ... and the pointers are not incremented This could happen due to a No more valid buffer data available for transmits b Buffer data available but DMA controller has excessive bandwidth requirements Bit is cleared by writing a 1 to this bit position 3 0 reserved Table 13 12 PISR Bit Definitions Physical Address 4050_0014 PISR Register AC 97 Controller Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 478: ...AIP This bit is read by software to check whether a CODEC IO cycle is currently in progress 0 No cycle is in progress and the act of reading the register sets this bit to 1 This reserves the right for the software driver to perform the IO cycle Once the cycle is complete this bit is automatically cleared Software can clear this bit by writing a 0 to this bit location if it decides not to perform a...

Page 479: ...Register 31 0 Processor DMA TxFIFO Written Processor DMA RxFIFO Read PCM Transmit FIFO PCM Receive FIFO Write Read Transmit Data Receive Data Table 13 15 MCCR Bit Definitions Physical Address 4050_0008 MCCR Register AC 97 Controller Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FEIE reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 480: ...31 5 reserved 4 FIFOE FIFO error FIFOE 0 No Receive FIFO error has occurred 1 A receive FIFO error occurred This bit is set if a receive FIFO overrun occurs In this case the FIFO pointers don t increment the incoming data from the AC link is not written into the FIFO and will be lost This could happen due to DMA controller having excessive bandwidth requirements and hence not being able to flush o...

Page 481: ... RxFIFO Read Mic in Receive FIFO MCDR Register 31 0 15 16 0x0000 Read Receive Data Table 13 18 MOCR Bit Definitions Physical Address 4050_0100 MOCR Register AC 97 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FEIE reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 4 reserved 3 FEIE FIFO Error ...

Page 482: ...causes an interrupt 0 No interrupt will occur even if bit 4 in the MISR is set 1 An interrupt will occur if bit 4 in the MISR is set 2 0 reserved Table 13 20 MOSR Bit Definitions Physical Address 4050_0110 MOSR Register AC 97 Controller Unit Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FIFOE reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 483: ...e Description 31 5 reserved 4 FIFOE FIFO error FIFOE 0 No Receive FIFO error has occurred 1 A receive FIFO error occurred This bit is set if a receive FIFO overrun occurs In this case the FIFO pointers don t increment the incoming data from the AC link is not written into the FIFO and will be lost This could happen due to DMA controller having excessive bandwidth requirements and hence not being a...

Page 484: ...hysical address for a Secondary Audio CODEC 0x4050 0300 Shift_Left_Once Internal 7 bit CODEC Register Address Processor physical address for a Primary Modem CODEC 0x4050 0400 Shift_Left_Once Internal 7 bit CODEC Register Address Processor physical address for a Secondary Modem CODEC 0x4050 0500 Shift_Left_Once Internal 7 bit CODEC Register Address In the equations Shift_Left_Once shifts the 7 bit ...

Page 485: ...50_042C 0x4050_052C 0x18 0x4050_0230 0x4050_0330 0x4050_0430 0x4050_0530 0x1A 0x4050_0234 0x4050_0334 0x4050_0434 0x4050_0534 0x1C 0x4050_0238 0x4050_0338 0x4050_0438 0x4050_0538 0x1E 0x4050_023C 0x4050_033C 0x4050_043C 0x4050_053C 0x20 0x4050_0240 0x4050_0340 0x4050_0440 0x4050_0540 0x22 0x4050_0244 0x4050_0344 0x4050_0444 0x4050_0544 0x24 0x4050_0248 0x4050_0348 0x4050_0448 0x4050_0548 0x26 0x40...

Page 486: ...02C4 0x4050_03C4 0x4050_04C4 0x4050_05C4 0x64 0x4050_02C8 0x4050_03C8 0x4050_04C8 0x4050_05C8 0x66 0x4050_02CC 0x4050_03CC 0x4050_04CC 0x4050_05CC 0x68 0x4050_02D0 0x4050_03D0 0x4050_04D0 0x4050_05D0 0x6A 0x4050_02D4 0x4050_03D4 0x4050_04D4 0x4050_05D4 0x6C 0x4050_02D8 0x4050_03D8 0x4050_04D8 0x4050_05D8 0x6E 0x4050_02DC 0x4050_03DC 0x4050_04DC 0x4050_05DC 0x70 0x4050_02E0 0x4050_03E0 0x4050_04E0 ...

Page 487: ...al Status Register 0x4050_0020 CAR CODEC Access Register 0x4050_0024 0x4050_003C reserved 0x4050_0040 PCDR PCM FIFO Data Register 0x4050_0044 0x4050_005C reserved 0x4050_0060 MCDR Mic in FIFO Data Register 0x4050_0064 0x4050_00FC reserved 0x4050_0100 MOCR Modem Out Control Register 0x4050_0104 reserved 0x4050_0108 MICR Modem In Control Register 0x4050_010C reserved 0x4050_0110 MOSR Modem Out Statu...

Page 488: ...13 36 Intel PXA255 Processor Developer s Manual AC 97 Controller Unit ...

Page 489: ...essor system memory The I2 S controller supports the normal I2 S and the MSB Justified I2 S formats Four or optionally five pins connect the controller to an external CODEC A bit rate clock which can use either an internal or an external source A formatting or Left Right control signal Two serial audio pins one input and one output The bit rate clock an optional system clock also sent to the CODEC...

Page 490: ...e configured either as an input or as an output To program the direction follow these steps 1 Program SYSUNIT s GPIO Direction Register GPDR See Section 4 1 3 2 GPIO Pin Direction Registers GPDR0 GPDR1 GPDR2 on page 4 8 for details regarding the GPDR 2 Program SYSUNIT s GPIO Alternate Function Select Register GAFR See Section 4 1 3 6 GPIO Alternate Function Register GAFR0_L GAFR0_U GAFR1_L GAFR1_U...

Page 491: ...A controller The processor uses programmed I O instructions to access the I2SC and can access the following types of data I2SC registers data All registers are 32 bits wide and are aligned to word boundaries See Section 14 6 for further details I2SC FIFO data An entry is placed into the Transmit FIFO by writing to the I2SC s Serial Audio Data register SADR Writing to SADR updates a Transmit FIFO e...

Page 492: ...nabled frames filled with 0s will be transmitted if the Transmit FIFO is still empty This will set a Transmit Under run status bit in SASR0 Step 3 can be executed to avoid this error condition Valid data is sent across the I2SLINK after filling the Transmit FIFO with at least one sample One sample consists of a 32 bit value with 16 bits each dedicated to a left and a right value Enabling the I2SLI...

Page 493: ...mory to the Transmit FIFO During the second condition the last valid sample is continuously sent across the I2SLINK until the I2SC is turned off by disabling the SACR0 ENB bit 14 3 5 Receive FIFO Errors A status bit is set during Receive Over run conditions If enabled this can trigger an interrupt For further details see Section 14 6 3 Section 14 6 6 and Section 14 6 5 During Receive Over run cond...

Page 494: ... buffers However single channel audio occupies a full 32 bit word per sample using either the upper or lower half of the word depending on whether it s considered a Left or Right sample 14 5 2 I2 S and MSB Justified Serial Audio Formats I2 S and MSB Justified are similar protocols for digitized stereo audio transmitted over a serial path The BITCLK supplies the serial audio bit rate the basis for ...

Page 495: ...w for the Left sample and high for the Right sample Also the MSB of each data sample lags behind the SYNC edges by one BITCLK cycle In the MSB Justified mode the SYNC is high for the Left sample and low for the Right sample Also the MSB of each data sample is aligned with the SYNC edges Figure 14 1 I2 S Data Formats 16 bits Figure 14 2 MSB Justified Data Formats 16 bits A8842 01 SYNC BITCLK Note T...

Page 496: ...ty resets all Receive FIFO pointers and also the counter that controls the I2SLINK resets the Receive FIFO does not affect the Transmit FIFO the output pin SYNC will not toggle de asserts all DMA requests any read accesses to the Data Register SADR by the processor or by the DMA controller is returned with zeros disables all interrupts Setting ENB to one does the following enables I2SLINK activity...

Page 497: ...hold Set to value 0 15 This value must be set to the threshold value minus 1 Receive DMA Request asserted whenever the Receive FIFO has RFTH 1 entries 11 8 TFTH Transmit FIFO interrupt or DMA threshold Set to value 0 15 This value must be set to the threshold value minus 1 Transmit DMA Request asserted whenever the Transmit FIFO has TFTH 1 entries 7 6 reserved 5 STRF Select Transmit or Receive FIF...

Page 498: ...s stored in a temporary register and is transferred to the BITCLK domain This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Table 14 4 FIFO Write Read table EFWR STRF Description 0 x Normal CPU DMA Write Read condition A write access to the Data Register writes a Transmit FIFO entry A read access to the Data Register reads out a Receive FIFO entry I2SLINK re...

Page 499: ...d Control Register I2S Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ENLBF DRPL DREC reserved AMSL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 6 reserved 5 ENLBF Enable I2 S MSB Interface Loop Back Function 0 I2S MSB Interface Loop Back Function is disabled 1 I2 S MSB Interface Loop B...

Page 500: ...t Mask Register is set Cleared by setting bit 6 of Serial Audio Interrupt Clear Register 5 TUR Transmit FIFO Under run 0 Transmit FIFO has not experienced an under run 1 I2 S attempted data read from an empty Transmit FIFO Can interrupt processor if bit 5 of Serial Audio Interrupt Mask Register is set Cleared by setting bit 5 of Serial Audio Interrupt Clear Register 4 RFS Receive FIFO Service Requ...

Page 501: ...finitions Physical Address 0x4040_0060 Serial Audio Clock Divider Register I2 S Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SADIV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 Bits Name Description 31 7 reserved 6 0 SADIV Audio clock divider Valid SADIV 6 0 are 000 1100 BITCLK of 3 072MHz 000 1101 BITCLK of 2...

Page 502: ...AIMR Bit Descriptions Physical Address 0x4040_0014 Serial Audio Interrupt Mask Register I2 S Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ROR TUR RFS TFS reserved Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 7 reserved 6 ROR Enable Receive FIFO Overrun condition based interrupt 5 TUR ...

Page 503: ... Register Summary All registers are word addressable 32 bits wide and hence increment in units of 0x00004 All I2SC registers are mapped in the address range of 0x4040_0000 through 0x4040_0080 as shown in Table 14 12 Figure 14 3 Transmit and Receive FIFO Accesses Through the SADR TxEntry0 TxEntry1 TxEntry2 TxEntry3 TxEntry15 31 Right Left 16 15 0 RxEntry0 RxEntry1 RxEntry2 RxEntry3 RxEntry15 31 Rig...

Page 504: ...ied Control Register 0x4040_0008 reserved 0x4040_000C SASR0 Serial Audio I2 S MSB Justified Interface and FIFO Status Register 0x4040_0014 SAIMR Serial Audio Interrupt Mask Register 0x4040_0018 SAICR Serial Audio Interrupt Clear Register 0x4040_001C through 0x4040_005C reserved 0x4040_0060 SADIV Audio clock divider register See Section 14 4 0x4040_0064 through 0x4040_007C reserved 0x4040_0080 SADR...

Page 505: ...must indicate whether to use MMC or SPI mode as the protocol to communicate with the MMC controller The MMC controller features Data transfer rates up to 20 Mbps A response FIFO Dual receive data FIFOs Dual transmit FIFOs Support for two MMCs in either MMC or SPI mode The MMC controller contains all card specific functions serves as the bus master for the MMC system and implements the standard int...

Page 506: ... the card s mode Response token formats are detailed The MultiMediaCard System Specification Version 2 1 Data data is transferred serially between the controller and the card in 8 bit blocks at rates up to 20 Mbps The format for the data token depends on the card s mode Table 15 2 shows the data token format for MMC mode and Table 15 3 shows the data token format for SPI mode In MMC mode all opera...

Page 507: ...pect to the processor The command and data tokens to be written are sent on the MMCMD signal and the response and read data tokens are received on the MMDAT signal Figure 15 4 shows a typical SPI mode timing diagram without a data token Figure 15 5 and Figure 15 6 show SPI mode read and write timing diagrams respectively Figure 15 2 MMC Mode Operation Without Data Token Figure 15 3 MMC Mode Operat...

Page 508: ...software must read and write the MMC controller registers and FIFOs to initiate communication to a card Figure 15 4 SPI Mode Operation Without Data Token Figure 15 5 SPI Mode Read Operation Figure 15 6 SPI Mode Write Operation Command MMCMD MMDAT Command Response from host to card from card to host from host to card Response Busy from card to host Command MMCMD MMDAT Command Response from host to ...

Page 509: ...e and the MMC bus It consists of control and status registers a 16 bit response FIFO that is eight entries deep two 8 bit receive data FIFOs that are 32 entries deep and two 8 bit transmit FIFOs that are 32 entries deep The registers and FIFOs are accessible by the software The MMC controller also enables minimal data latency by buffering data and generating and checking CRCs Refer to Section 15 4...

Page 510: ...he MMC card must be initialized by sending 80 clocks to it on the MMCLK signal To initialize the MMC card set the MMC_CMDAT INIT bit to a 1 This sends 80 clocks before the current command in the MMC_CMD register This function is useful for acquiring new cards that have been inserted on the bus Chip selects are not asserted during the initialization sequence After the 80 clock initialization sequen...

Page 511: ... number of blocks that will be erased during the write operation and is fixed for each MMC card A block is the number of bytes to be transferred The MMC mode supports these data transfer modes Single block read write in single block mode a single block of data is transferred The starting address is specified in the command token of the read or write command used The software must set the block siz...

Page 512: ... tokens but these bits are ignored by the card and the controller In write data transfers the data is suffixed with an 8 bit CRC status token from the card As in MMC mode the card may indicate that it is busy by pulling the MMDAT line low after the status token In read data transfers the card may respond with the data or a data error token one byte long 15 2 5 Error Detection The MMC controller de...

Page 513: ...transmitted or accessed When the receive FIFOs are empty and the MMC_STAT DATA_TRAN_DONE is set software may stop the clock The software can specify the clock divisor of the 20 Mhz clock by setting the MMC_CLKRT register The clock rate may be set as 20 Mhz 1 2 of 20 Mhz 10 Mhz 1 4 of 20 Mhz 5 Mhz 1 8 of 20 Mhz 2 5 Mhz 1 16 of 20 Mhz 1 25 Mhz 1 32 of 20 Mhz 625 khz 1 64 if 20 Mhz 312 5 khz The cont...

Page 514: ...etween the software and MMC bus At any time while the software has read access to one of the FIFOs the MMC bus has write access to the other FIFO For purposes of an example the FIFOs are called RXFIFO1 and RXFIFO2 After a reset or at the beginning of a command sequence both FIFOs are empty and the software has read access to RXFIFO1 and the MMC has write access to RXFIFO2 When RXFIFO2 becomes full...

Page 515: ...her FIFO For purposes of an example the FIFOs are called TXFIFO1 and TXFIFO2 After a reset or at the beginning of a command sequence both FIFOs are empty and the software has write access to TXFIFO1 and the MMC has read access to TXFIFO2 When TXFIFO1 becomes full and TXFIFO2 is empty the FIFOs swap and the software has write access to TXFIFO2 and the MMC has read access to TXFIFO1 When TXFIFO2 bec...

Page 516: ...ee times then write nine more bytes For the DMA use three descriptors of 32 bytes and 32 byte bursts and one descriptor of nine more bytes and 16 or 32 byte bursts and program the descriptor to set an interrupt for the software to write MMC_PRTBUF BUF_PART_FULL bit 15 2 8 4 DMA and Program I O The software may communicate to the MMC controller via the DMA or program I O To access the FIFOs with th...

Page 517: ...MMC_SPI MMC_RESTO 4 Start the clock 5 Write 0x7b to the MMC_I_MASK register and wait for and verify the MMC_I_REG END_CMD_RES interrupt 6 Read the MMC_RES FIFO and MMC_STAT registers Some cards may become busy as the result of a command The software may wait for the card to become not busy by writing the MMC_I_MASK register and waiting for the MMC_I_REG PRG_DONE interrupt or the software can start...

Page 518: ...nsactions in all the basic modes single block multiple blocks and stream modes 15 3 2 1 Block Data Write In a single block data write a block of data is written to a card In a multiple block write the controller performs multiple single block write data transfers on the MMC bus After turning the clock on to start the command sequence the software must program the DMA to fill the MMC_TXFIFO write 3...

Page 519: ... the data transmission the controller turns the clock off Once the software empties the FIFO to which it is connected the controller turns the clock back on In a block data read the following parameters must be specified The data transfer is a read The block length if the block length is different from the previous block data transfer or this is the first time that the parameter is being specified...

Page 520: ...ds the stop transmission command In a stream data read the following parameters must be specified The data transfer is a read The data transfer is in stream mode The block length if the block length is different from the previous block data transfer or this is the first time that the parameter is being specified The number of blocks to be transferred as 0xffff The receive data time out period 15 3...

Page 521: ... a data error token is received the controller will stop the transmission and update the status register 15 4 MultiMediaCard Controller Operation The software directs all communication between the card and the controller The operations shown in the preceding sections are valid for MMC mode only 15 4 1 Start and Stop Clock The set of registers is accessed by stopping the clock writing the registers...

Page 522: ...nmask the MMC_I_REG END_CMD_RES interrupt 7 Start the clock as described in Section 15 4 1 The software must not make changes in the set of registers until the end of the command and response sequence after the clock is turned on After the clock is turned on the software must wait for the MMC_I_REG END_CMD_RES interrupt which indicates that the command and response sequence is finished and the res...

Page 523: ...register must be set 3 Set MMC_I_MASK register to 0x1e and wait for MMC_I_REG DATA_TRAN_DONE interrupt 4 Set MMC_I_MASK to 0x1d 5 Wait for MMC_I_REG PRG_DONE interrupt This interrupt indicates that the card has finished programming Software may wait for MMC_I_REG PRG_DONE or start another command sequence on a different card 6 Read the MMC_STAT register to verify the status of the transaction i e ...

Page 524: ...e block write mode is similar to the single block write mode except that multiple blocks of data are transferred Each block is the same length All the registers are set as they are for the single block write except that the MMC_NOB register is set to the number of blocks to be written The multiple block write mode also requires a stop transmission command CMD12 after the data is transferred to the...

Page 525: ... set 3 Set MMC_I_MASK to 0x77 and wait for MMC_I_REG STOP_CMD interrupt 4 Set the command registers for a stop transaction command CMD12 5 Wait for a response to the stop transaction command as described in Section 15 4 4 6 Set MMC_I_MASK to 0x1e 7 Wait for MMC_I_REG DATA_TRAN_DONE interrupt 8 Set MMC_I_MASK to 0x1d 9 Wait for MMC_I_REG PRG_DONE interrupt This interrupt indicates that the card has...

Page 526: ...stop transaction command CMD12 If the DMA is being used the last descriptor must set the DMA to send an interrupt to signal that all the data has been read 4 Wait for a response to the stop transaction command as described in Section 15 4 4 5 Set MMC_I_MASK to 0x1e 6 Wait for MMC_I_REG DATA_TRAN_DONE interrupt 7 Read the MMC_STAT register to verify the status of the transaction i e CRC error statu...

Page 527: ...10 Start the MMC clock 11 reserved Table 15 6 MMC_STAT Bit Definitions Sheet 1 of 2 Physical Address 0x4110_0004 MMC_STAT Register MultiMediaCard Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved END_CMD_RES PRG_DONE DATA_TRAN_DONE reserved CLK_EN RECV_FIFO_FULL XMIT_FIFO_EMPTY RES_CRC_ERR SPI_READ_ERROR_TOKEN CRC_READ_ERROR CRC_WRITE_ERR...

Page 528: ...en 0 SPI data error token has not been received 1 SPI data error token has been received 3 CRC_READ_ ERROR CRC Read Error 0 No error on received data 1 CRC error occurred on received data 2 CRC_WRITE_ ERROR CRC Write Error 0 No error on transmission of data 1 Card observed erroneous transmission of data 1 TIME_OUT_R ESPONSE Time Out Response 0 Card response has not timed out 1 Card response timed ...

Page 529: ...1 10 MHz clock 1 2 of 20 MHz clock 010 5 MHz clock 1 4 of 20 MHz clock 011 2 5 MHz clock 1 8 of 20MHz clock 100 1 25MHz clock 1 16 of 20 MHz clock 101 0 625 MHz clock 1 32 of 20 MHz clock 110 0 3125 MHz clock 1 64 of 20 MHz clock 111 reserved Table 15 8 MMC_SPI Bit Definitions Sheet 1 of 2 Physical Address 0x4110_000c MMC_SPI Register MultiMediaCard Controller Bit 31 30 29 28 27 26 25 24 23 22 21 ...

Page 530: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description Table 15 9 MMC_CMDAT Bit Definitions Sheet 1 of 2 Physical Address 0x4110_0010 MMC_CMDAT Register MultiMediaCard Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MMC_DMA_EN INIT BUSY STREAM_BLOCK WRITE READ DATA_EN RESPONSE_FORMAT 1 0 Reset 0 0 0 0 0 0...

Page 531: ...includes a data transfer 1 0 RESPONSE_ FORMAT 1 0 These bits specify the response format for the current command 00 No response in MMC mode Not supported in SPI mode 01 Format R1 R1b R4 and R5 in MMC mode Format R1 and R1b in SPI mode 10 Format R2 in MMC mode Format R2 in SPI mode 11 Format R3 in MMC mode Format R3 in SPI mode Table 15 9 MMC_CMDAT Bit Definitions Sheet 2 of 2 Physical Address 0x41...

Page 532: ...o calculate the value for READ_TO The default value is 0xffff which corresponds to 838 848 ms This is a read write register Ignore reads from reserved bits Write zeros to reserved bits Time out Delay MMC_RDTO READ_TO 256 20MHz MMC_RDTO READ_TO 128 107 sec Table 15 11 MMC_RDTO Register Physical Address 0x4110_0018 MMC_RDTO Register MultiMediaCard Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 533: ...ions Physical Address 0x4110_001c MMC_BLKLEN Register MultiMediaCard Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BLK_LEN Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 10 reserved 9 0 BLK_LEN Number of bytes in the block Table 15 13 MMC_NOB Bit Definitions Physical Address 0x4110_0020 ...

Page 534: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BUF_PART_FULL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31 1 reserved 0 BUF_PART_F ULL Buffer Partially Full 0 Buffer is not partially full 1 Buffer is partially full and must be swapped to the other transmit buffer Software must clear this bit before send...

Page 535: ...uest 0 Not masked 1 Masked 4 CLK_IS_ OFF Clock Is Off 0 Not masked 1 Masked 3 STOP_CMD Ready for Stop Transaction Command 0 Not masked 1 Masked 2 END_CMD_R ES End Command Response 0 Not masked 1 Masked 1 PRG_DONE Programming Done 0 Not masked 1 Masked 0 DATA_TRAN_ DONE Data Transfer Done 0 Not masked 1 Masked Table 15 15 MMC_I_MASK Bit Definitions Sheet 2 of 2 Physical Address 0x4110_0028 MMC_I_MA...

Page 536: ...om MMC_RXFIFO FIFO Cleared after each read but immediately set again unless the FIFO is empty 4 CLK_IS_ OFF Clock Is Off 0 MMC clock has not been turned off 1 MMC clock has been turned off due to stop bit in STRP_CLK register Cleared by the MMC_STAT CLK_EN bit when the clock is started 3 STOP_CMD For stream mode writes 0 MMC is not ready for the stop transmission command 1 MMC is ready for the sto...

Page 537: ...nce and cannot be changed 6 reserved Transmission bit in command sequence and cannot be changed 5 0 CMD_INDEX Command index see Table 15 18 Table 15 18 Command Index Values Sheet 1 of 3 CMD INDEX COMM AND MODE ABBREVIATION 000000 CMD0 MMC SPI GO_IDLE_STATE 000001 CMD1 MMC SPI SEND_OP_COND 000010 CMD2 MMC ALL_SEND_CID 000011 CMD3 MMC SET_RELATIVE_ADDR 000100 CMD4 MMC SET_DSR 000101 CMD5 reserved 00...

Page 538: ...ECTOR_END 100010 CMD34 MMC SPI UNTAG_SECTOR 100011 CMD35 MMC SPI TAG_ERASE_GROUP_START 100100 CMD36 MMC SPI TAG_ERASE_GROUP_END 100101 CMD37 MMC SPI UNTAG_ERASE_GROUP 100110 CMD38 MMC SPI ERASE 100111 CMD39 MMC FAST_IO 101000 CMD40 MMC GO_IRQ_STATE 101001 CMD41 reserved 101010 CMD42 MMC SPI LOCK_UNLOCK 101011 CMD43 reserved 101100 CMD44 reserved 101101 CMD45 reserved 101110 CMD46 reserved 101111 C...

Page 539: ...D62 MMC reserved for manufacturer 111111 CMD63 MMC reserved for manufacturer Table 15 18 Command Index Values Sheet 3 of 3 CMD INDEX COMM AND MODE ABBREVIATION Table 15 19 MMC_ARGH Bit Definitions Physical Address 0x4110_0034 MMC_ARGH Register MultiMediaCard Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ARG_H Reset 0 0 0 0 0 0 0 0 0 0...

Page 540: ... software and is read on 8 bit boundaries The eight bits of data are read on a 32 bit boundary and occupying the least significant byte lane 7 0 This is a read only register Ignore reads from reserved bits Table 15 21 MMC_RES FIFO Entry Physical Address 0x4110_003c MMC_RES FIFO Entry MultiMediaCard Controller Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 541: ... 11 10 9 8 7 6 5 4 3 2 1 0 reserved WRITE_DATA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Bits Name Description 31 16 reserved 7 0 WRITE_DATA One byte of write data Table 15 24 MMC Controller Registers Sheet 1 of 2 Address Name Description 0x4110_0000 MMC_STRPCL Control to start and stop MMC clock 0x4110_0004 MMC_STAT MMC status register read only 0x4110_0008 MMC_CLKRT M...

Page 542: ...anual MultiMediaCard Controller 0x4110_003c MMC_RES Response FIFO read only 0x4110_0040 MMC_RXFIFO Receive FIFO read only 0x4110_0044 MMC_TXFIFO Transmit FIFO write only Table 15 24 MMC Controller Registers Sheet 2 of 2 Address Name Description ...

Page 543: ...Protocol Motorola Serial Peripheral Interface SPI protocol National Semiconductor Microwire Programmable Serial Protocol PSP The NSSP operates as full duplex devices for the TI Synchronous Serial Protocol SPI and PSP protocols and as half duplex devices for the Microwire protocol The FIFOs can be loaded or emptied by the CPU using programmed I O or DMA burst transfers 16 2 Features Supports the TI...

Page 544: ... by the receive FIFO is automatically sent to the SSP Data Register 16 4 1 Processor and DMA FIFO Access The CPU or DMA accesses data through the SSP transmit and receive FIFOs A CPU access takes the form of programmed I O transferring one FIFO entry per access The FIFO are seen as one 32 bit location by the processor CPU accesses are normally triggered by an SSSR interrupt and are always 32 bits ...

Page 545: ...mory map perspective both reads and writes are at the same address The FIFOs are 16 samples deep by one word wide 16 4 2 Trailing Bytes in the Receive FIFO When the number of samples in the receive FIFO is less than the trigger threshold and no additional data is received the remaining bytes are called trailing bytes Trailing bytes must be handled by the processor Trailing bytes are identified via...

Page 546: ...CLK function and use varies between each protocol For TI Synchronous Serial Protocol data sources switch transmit data on the rising edge of SSPSCLK and sample receive data on the falling edge Master and slave modes are supported For SPI the SSP lets programmers select which edge of SSPSCLK to use for switching transmit data and for sampling receive data In addition users can move the phase of SSP...

Page 547: ... pulsed high for one SSPSCLK period and the value to be transmitted is transferred from the transmit FIFO to the transmit logic serial shift register On the next rising edge of SSPSCLK the most significant bit of the four to 32 bit data frame is shifted to the SSPTXD pin Likewise the MSB of the received data is shifted onto the SSPRXD pin by the off chip serial slave device Both the SSP and the of...

Page 548: ...g edge of SSPSCLK after the last bit latched at its destination and the completed incoming word is shifted into the incoming FIFO The peripheral can drive SSPRXD to a high impedance state after sending the last bit of the frame SSPTXD retains the last value transmitted when the controller goes into idle mode unless the SSP is disabled or reset which forces SSPTXD low For back to back transfers fra...

Page 549: ...nsumption this pin must not float 16 4 3 2 1 Serial Clock Phase SPH The phase relationship between the SSPSCLK and the serial frame SSPSFRM pins when the Motorola SPI protocol is selected is controlled by SSCR1 SPH When SPH is cleared SSPSCLK remains in its inactive or idle state as determined by SSCR1 SPO for one full cycle after SSPSFRM is asserted low at the beginning of a frame SSPSCLK continu...

Page 550: ...O and SSCR1 SPH to opposite values one set and the other cleared transmit data is driven on the rising edge of SSPSCLK and receive data is latched on the falling edge of SSPSCLK Note SSCR1 SPH is ignored for all data frame formats except for the Motorola SPI protocol Figure 16 6 shows the pin timing for all four programming combinations of SSCR1 SPO and SSCR1 SPH The SSCR1 SPO inverts the polarity...

Page 551: ... bit period after the last command bit the peripheral returns the serial data requested most significant bit first on SSPRXD Data transitions on the falling edge of SSPSCLK and is sampled on the rising edge The last falling edge of SSPSCLK coincides with the end of the last data bit on SSPRXD and SSPSCLK remains low after that if it is the only word or the last word of the transfer SSPSFRM de asse...

Page 552: ...al clock sub modes depending on the SSPSCLK edges selected for driving data and sampling received data and the selection of idle state of the clock For the PSP the idle and disable modes of the SSPTXD SSPSCLK and SSPSFRM are programmable via SSPSP ETDS SSPSP SCMODE and SSPSP SFRMP When transmit data is ready the SSPSCLK remains in its idle state for the number of serial clock SSPSCLK clock periods...

Page 553: ... of SSPSFRM receive data is simultaneously driven from the peripheral on SSPRXD MSB first Data transitions on SSPSCLK based on the serial clock mode selected and are sampled by the controller on the opposite edge When the SSP is a master to the frame sync SSPSFRM and a slave to the clock SSPSCLK at least three extra clocks are needed at the beginning and end of each block of transfers to synchroni...

Page 554: ...nsfers Table 16 2 Programmable Serial Protocol PSP Parameters Symbol Definition Range Units Serial clock mode SSPSP SCMODE Drive Sample SSPSCLK Idle 0 Fall Rise Low 1 Rise Fall Low 2 Rise Fall High 3 Fall Rise High Serial frame polarity SSPSP SFRMP High or Low T1 Start delay SSPSP STRTDLY 0 7 Clock period T2 Dummy start SSPSP DMYSTRT 0 3 Clock period T3 Data size SSCR0 EDSS and SSCR0 DSS 4 32 Cloc...

Page 555: ...n SSCR1 TTE is 0 the SSP behaves as described in Section 16 4 3 1 If SSCR1 TTE is 1 and SSCR1 TTELP is 0 SSPTXD is driven with the MSB at the first rising edge of SSPSCLK after SSPSFRM is asserted SSPTXD is Hi Z after the falling edge of SSPSCLK for the LSB 1 clock edge after the clock edge that starts the LSB Figure 16 11shows the pin timing for this mode If SSCR1 TTE is 1 and SSCR1 TTELP is 1 SS...

Page 556: ...TTELP must be 0 for Motorola SPI 16 4 4 3 National Semiconductor Microwire When SSCR1 TTE is 0 the SSP behaves as described in Section 16 4 3 3 If SSCR1 TTE is 1 SSPTXD is driven at the same clock edge that the MSB is driven SSPTXD is Hi Z after the next rising edge of SSPSCLK for the LSB 1 clock edge after the clock edge that starts the LSB Figure 16 14 shows the pin timing for this mode Figure 1...

Page 557: ...ster to frame SSPTXD is Hi Z two clock edges after the clock edge that drives the LSB This occurs even if the SSP is a master of clock and this clock edge does not appear on the SSPSCLK Figure 16 16 shows the pin timing for this mode Figure 16 14 National Semiconductor Microwire with SSCR1 TTE 1 A9977 01 SSPRXD SSPSFRM SSPSCLK SSPTXD 4 to 32 Bits Bit 7 or Bit 15 8 or 16 Bit Control Bit 0 Bit N Bit...

Page 558: ...ock then the device driving SSPSCLK must provide another clock edge Figure 16 17 shows the pin timing for this mode Figure 16 16 PSP mode with SSCR1 TTE 1 and SSCR1 TTELP 0 master to frame A9979 01 MSB Undefined Undefined T1 T2 T3 T4 LSB MSB LSB T6 T5 SSPSCLK when SCMODE 0 SSPSCLK when SCMODE 1 SSPSCLK when SCMODE 2 SSPSCLK when SCMODE 3 SSPSFRM when SFRMP 1 SSPSFRM when SFRMP 0 SSPTXD SSPRXD Figu...

Page 559: ...g the DMA is as Program the total number of transmit and receive byte lengths burst sizes and peripheral width Program DCMD WIDTH to 0b01 for SSP formats of 8 bits or less to 0b10 for SSP formats of 9 to 16 bits to 0b11 for SSP formats of more than 16 bits When DCMD WIDTH is 0b01 1 byte then the DMA burst size must be configured for 8 or 16 bytes per burst Set the preferred values in the SSP contr...

Page 560: ...the receive FIFO A write cycle or burst write puts successive words into the SSP write register and then into the transmit FIFO A read cycle or burst read takes data from the SSP read register and the receive FIFO reloads it with available data bits it has stored Do not increment the address using read and write DMA bursts Besides showing the state of the FIFO buffers the status register shows whe...

Page 561: ...t baud rates using polled interrupt mode is insufficient to keep the FIFO filled You must use DMA mode NOTE Software must not change SCR when the SSPSCLK is enabled because doing so causes the SSPSCLK frequency to immediately change Serial bit rate SSP Clock SCR 1 7 SSE SYNCHRONOUS SERIAL PORT ENABLE DISABLE Enables and disables all SSP operations When the port is disabled all of its clocks can be...

Page 562: ...SS are used to determine the receive data size When data is programmed to be less than 32 bits the FIFO must be programmed right justified EDSS DSS Data Size EDSS DSS Data Size 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111 17 bit data 18 bit data 19 bit data 20 bit data 21 bit data 22 bit data 23 bit ...

Page 563: ...at the same clock edge that the MSB is driven and SSPTXD is Hi Z after the next rising edge of SSPSCLK for the LSB 1 clock edge after the clock edge that starts the LSB For SPI SSPTXD is Hi Z whenever SSPFRM is deasserted For TI SSP format SSPTXD is driven with the MSB at the first rising edge of SSPSCLK after SSPSFRM is asserted and is Hi Z after the falling edge of SSPSCLK for the LSB 1 clock ed...

Page 564: ...tion is selected for the port this bit has precedence over the GPIO direction bit For example the GPIO pin is an input if SFRMDIR 1 Alternately the GPIO pin is an output if SFRMDIR 0 0 Master mode the port generates SSPSFRM internally acts as the master and drives SSPSFRM 1 Slave mode the port acts as a slave receives SSPSFRM from an external device 23 RWOT RECEIVE WITH OUT TRANSMIT Puts the SSP i...

Page 565: ...mines the number of half serial clock periods that SSPSFRM is delayed from the start of the transfer The programed value sets the number of half SSPSCLK cycles from the time TXD RXD starts being driven to the time SSPSFRM is asserted from 0 to 74 8 7 DMYSTRT DUMMY START Determines the number of SSPSCLK cycles after STRTDLY that precede the transmitted SSPTXD or received data SSPRXD 6 4 STRTDLY THR...

Page 566: ...0b00 Data Driven Falling Data Sampled Rising Idle State Low 0b01 Data Driven Rising Data Sampled Falling Idle State Low 0b10 Data Driven Rising Data Sampled Falling Idle State High 0b11 Data Driven Falling Data Sampled Rising Idle State High Table 16 5 SSPSP Bit Definitions Sheet 2 of 2 0x4140_002C SSPSP Network SSP Serial Port Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ...

Page 567: ... is not empty One interrupt signal is sent to the interrupt controller for each SSP These events can cause an interrupt Receiver time out Receive FIFO overrun Receive FIFO request Transmit FIFO request Table 16 7 SSITR Bit Definitions 0x4140_000C SSITR Network SSP Serial Port Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TROR TRFS TTFS reserved ...

Page 568: ... detected the SSPSFRM signal asserted at an incorrect time This bit will cause an interrupt if SSCR1 BCE is set The SSP will ignore the current sample and the next sample in order to re synchronize with the master Write one to clear this bit 0 SSPSFRM has not been asserted out of synchronization 1 SSPSFRM has been asserted out of synchronization 22 CSS CLOCK SYNCHRONIZATION STATUS A read only bit ...

Page 569: ...P register bit The setting of ROR does not generate any DMA service request Clearing this bit resets its interrupt request Write one to clear this bit 0 Receive FIFO has not experienced an overrun 1 Attempted data write to full receive FIFO request Interrupt 6 RFS RECEIVE FIFO SERVICE REQUEST Indicates that the receive FIFO requires service to prevent an overrun RFS is set when the number of valid...

Page 570: ...or receiving data and is cleared when the port is idle or disabled This bit does not generate an Interrupt Software must wait for the Tx Fifo to empty first and then wait for the BSY bit to be cleared at the end of a data transfer 0 SSP is idle or disabled 1 SSP currently transmitting or receiving a frame 3 RNE RECEIVE FIFO NOT EMPTY Indicates that the receive FIFO contains one or more entries of ...

Page 571: ...CR1 MWDS cleared the most significant bits are ignored Similarly if the size for the Transmit data is 16 bits SSCR1 MWDS set the most significant 16 bits are ignored SSCR0 DSS controls the Receive data size Both FIFOs are cleared when the port is reset or by clearing SSCR0 SSE This is a read write register Ignore reads from reserved bits Write zeros to reserved bits 16 6 Network SSP Serial Port Re...

Page 572: ...16 30 Intel PXA255 Processor Developer s Manual Network SSP Serial Port ...

Page 573: ... on data characters received from the processor The processor can read the UART s complete status during functional operation Status information includes the type and condition of transfer operations and error conditions parity overrun framing or break interrupt associated with the UART The HWUART operates in FIFO or non FIFO mode In FIFO mode a 64 byte transmit FIFO holds data from the processor ...

Page 574: ...ions clear to send nCTS and request to send nRTS Autoflow capability controls data I O without generating interrupts nRTS output controlled by UART receiver FIFO nCTS input from modem controls UART transmitter Fully programmable serial interface 5 6 7 or 8 bit characters Even odd and no parity detection 1 1 5 or 2 stop bit generation Baud rate generation up to 921 Kbps False start bit detection 64...

Page 575: ...is enabled an interrupt is generated nCTS has no effect on the transmitter The user can program the UART to interrupt the processor when DCTS changes state The programmer can then stall the outgoing data stream by starving the transmit FIFO or disabling the UART with the Interrupt Enable register IER NOTE If UART transmission is stalled by disabling the UART the user will not receive an MSR interr...

Page 576: ...e FIFO is 64 bytes deep and 11 bits wide Three bits are used for tracking errors The UART can use NRZ coding to represent individual bit values NRZ coding is enabled when Interrupt Enable register IER bit 5 IER 5 is set to high A one is represented by a line transition and a zero is represented by no line transition Figure 17 2 shows the data byte 0b 0100 1011 in NRZ coding The LSB is transmitted ...

Page 577: ... in this interval The most recent FIFO read was performed more than four continuous character times ago After the processor reads one character from the receive FIFO or a new start bit is received the timeout interrupt is cleared and the timeout is reset If a timeout interrupt has not occurred the timeout is reset when a new character is received or the processor reads the receive FIFO 17 4 2 1 3 ...

Page 578: ...must set DCSR StopIrqEn to generate an interrupt if a stopped channel occurs 17 4 2 5 DMA Error Handling An error interrupt is used when DMA requests are enabled The interrupt is generated when LSR bit 7 is set to 1 This happens when a receive DMA request is not generated and the receive FIFO has an error The error interrupt tells the processor to handle the data in the receive FIFO through progra...

Page 579: ...amount of data in the receive FIFO is below the programmable trigger threshold value When the amount of data in the receive FIFO reaches the programmable trigger threshold nRTS is deasserted It is asserted once again when enough bytes are removed from the FIFO to lower the data level below the trigger threshold When in full or half autoflow mode nCTS is asserted by the remote receiver when the rec...

Page 580: ... baud rate detection is not supported with IrDA slow infrared mode See Section 17 5 8 for more information on auto baud 17 4 5 Slow Infrared Asynchronous Interface The Slow Infrared SIR interface supports two way wireless communication that uses infrared transmission The SIR provides a transmit encoder and receive decoder to support a physical link that conforms to the Infrared Data Association Se...

Page 581: ... of each zero bit The shorter infrared pulse generated when XMODE is set reduces the LED s power consumption At 2400 bps the LED is normally on for 78 µs for each zero bit that is transmitted When XMODE is set the LED is on only 1 6 µs as show in Figure 17 4 To prevent transmitter LED reflection feed back to the receiver disable the IR receiver decoder when the IR transmit encoder transmits data a...

Page 582: ...FO mode a write to the THR puts data into the end of the FIFO The data at the front of the FIFO is loaded to the TSR when that register is empty This is a write only register Write zeros to reserve bits 17 5 3 Divisor Latch Registers DLL and DLH The HWUART contains a programmable baud rate generator that can take the 14 7456 MHz fixed input clock and divide it by a number that is between 1 and 216...

Page 583: ... by setting the appropriate bit The character timeout indication interrupt is separated from the received data available interrupt to ensure that the processor and the DMA controller do not service the receive FIFO at the same time When a character timeout indication interrupt occurs the processor must handle the data in the receive FIFO through programmed I O BaudRate 14 7456 MHz 16xDivisor Table...

Page 584: ... 0 0 0 0 0 0 0 0 Bits Name Description 31 8 reserved 7 DMAE DMA REQUESTS ENABLE 0 DMA requests are disabled 1 DMA requests are enabled 6 UUE UART Unit Enable 0 the unit is disabled 1 the unit is enabled 5 NRZE NRZ CODING ENABLE NRZ encoding decoding is only used in UART mode not in infrared mode If the slow infrared receiver or transmitter is enabled NRZ coding is disabled 0 NRZ coding disabled 1 ...

Page 585: ... no encoded interrupt is pending regardless of the state of the other 3 bits nIP has no effect or association with IIR ABL which asserts deasserts independently of nIP This is a read only register Ignore reads from reserved bits Table 17 7 Interrupt Conditions Priority Level Interrupt origin 1 highest Receiver line status One or more error bits were set 2 Received data is available In FIFO mode tr...

Page 586: ... 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FIFOES reserved ABL TOD IID nIP Reset 0 0 0 0 0 0 1 Bits Name Description Table 17 9 Interrupt Identification Register Decode Sheet 1 of 2 Interrupt ID bits Interrupt SET RESET Function 3 2 1 0 Priority Type Source RESET Control nIP 0 0 0 1 None No interrupt is pending IID 11 0 1 1 0 Highest Receiver Line Status Overrun error par...

Page 587: ... reserved TIL RESETTF RESETRF TRFIFOE Reset 0 0 0 0 0 0 Bits Name Description 31 8 reserved 7 6 ITL Interrupt Trigger Level threshold When the number of bytes in the receiver FIFO equals the interrupt trigger threshold programmed into this field and the received data available interrupt is enabled via the IER an interrupt is generated and appropriate bits are set in the IIR The receive DMA request...

Page 588: ... and Receive FIFO Enable TRFIFOE enables disables the transmitter and receiver FIFOs When TRFIFOE 1 both FIFOs are enabled FIFO Mode When TRFIFOE 0 the FIFOs are both disabled non FIFO Mode Writing a 0 to this bit clears all bytes in both FIFOs When changing from FIFO mode to non FIFO mode and vice versa data is automatically cleared from the FIFOs This bit must be 1 when other bits in this regist...

Page 589: ...d rate If auto baud mode ABR ABE Section 17 5 8 and auto baud interrupts ABR ABLIE are enabled the UART interrupts the processor with the auto baud lock interrupt IIR ABL Section 17 5 5 after it has written the count value into the ACR The value is written regardless of the state of the auto baud UART program bit ABR ABUP Table 17 12 ABR Bit Definitions Physical Address 0x4160_0028 Autobaud Contro...

Page 590: ...tions Sheet 1 of 2 Physical Address 0x4160_000C Line Control Register LCR PXA255 Processor Hardware UART Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DLAB SB STKYP EPS PEN STB WLS Reset 0 0 0 0 0 0 0 0 Bits Name Description 31 8 reserved 7 DLAB DIVISOR LATCH ACCESS BIT Must be set to access the divisor latches of the baud rate generator during ...

Page 591: ...d LSR 4 1 bits are set until software reads the LSR See Section 17 4 2 3 for details on using the DMA to receive data This is a read only register Ignore reads from reserved bits 4 EPS EVEN PARITY SELECT Even parity select bit If PEN 0 EPS is ignored 0 Sends or checks for odd parity 1 Sends or checks for even parity 3 PEN PARITY ENABLE Enables a parity bit to be generated on transmission or checke...

Page 592: ...ransmit Shift register the Transmit Holding register or the FIFO 1 All the data in the transmitter has been shifted out 5 TDRQ TRANSMIT DATA REQUEST Indicates that the UART is ready to accept a new character for transmission In addition this bit causes the UART to issue an interrupt to the processor when the transmit data request interrupt enable is set high and generates the DMA request to the DM...

Page 593: ...t PE is set when a parity error is detected and is cleared when the processor reads the LSR In FIFO mode PE shows a parity error for the character at the front of the FIFO not the most recently received character 0 No parity error 1 Parity error has occurred 1 OE OVERRUN ERROR In non FIFO mode OE indicates that data in the Receive Buffer register was not read by the processor before the next chara...

Page 594: ...ins nRTS and nDTR are forced to their inactive state Coming out of the loopback mode may result in unpredictable activation of the delta bits bits 3 0 in the Modem Status register MSR It is recommended that MSR is read once to clear the delta bits in the MSR Loopback mode must be configured before the UART is enabled MCR RTS is connected to the Modem Status register CTS bit This allows software to...

Page 595: ...odem status interrupt is generated if IER MIE is set This is a read only register Ignore reads from reserved bits 1 RTS REQUEST TO SEND Controls the status of the nRTS pin when the AFE bit is clear When AFE is set switches between full autoflow and half autoflow Autoflow mode disabled 0 nRTS pin is 1 1 nRTS pin is 0 Autoflow mode enabled 0 Auto RTS disabled Auto flow works only with auto CTS 1 Aut...

Page 596: ...to send nCTS input Equivalent to MCR RTS if MCR LOOP is set 0 nCTS pin is 1 1 nCTS pin is 0 3 1 reserved 0 DCTS DELTA CLEAR TO SEND 0 No change in nCTS pin since last read of MSR 1 nCTS pin has changed state Table 17 17 MSR Bit Definitions Sheet 2 of 2 Physical Address 0x4160_0018 Modem Status Register MSR PXA255 Processor Hardware UART Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ...

Page 597: ... Transmit pulse width is 3 16 of a bit time wide 1 Transmit pulse width is 1 6 µs 1 RCVEIR RECEIVER SIR ENABLE When RCVEIR is set the signal from the RXD pin is processed by the IrDA decoder before it is fed to the UART If RCVEIR is cleared then all clocking to the IrDA decoder is blocked and the RXD pin is fed directly to the UART 0 Receiver is in UART mode 1 Receiver is in infrared mode 0 XMITIR...

Page 598: ...em Status Register MSR read only 0x4160_001C X HWSPR Scratchpad Register SCR read write 0x4160_0020 X HWISR Infrared Selection Register ISR read write 0x4160_0024 X HWFOR Receive FIFO Occupancy Register FOR read only 0x4160_0028 X HWABR Auto Baud Control Register ABR read write 0x4160_002C X HWACR Auto Baud Count Register ACR 0x4160_0000 1 HWDLL Divisor Latch Registers DLL and DLH low byte read wr...

Page 599: ...Intel PXA255 Processor Developer s Manual 17 27 Hardware UART ...

Page 600: ......

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