Intel PXA255, Developer'S Manual

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17-2 Intel® PXA255 Processor Developer’s Manual
Hardware UART
— Non-Return-to-Zero (NRZ) encoding/decoding function
— 64 byte transmit/receive FIFO buffers
— Programmable receive FIFO trigger threshold
— Auto baud-rate detection
— Auto flow
•
Maximum baud rate of 921,600 bps.
•
Ability to add or delete standard asynchronous communications bits (start, stop, and parity) in
the serial data
•
Independently controlled transmit, receive, line status, and data set interrupts
•
Programmable baud rate generator that allows the internal clock to be divided by 1 to 2
16
–1 to
generate an internal 16X clock. This clock can be used to drive the internal transmitter and
receiver logic.
•
Modem control functions – clear to send (nCTS) and request to send (nRTS)
•
Autoflow capability controls data I/O without generating interrupts:
— nRTS (output) controlled by UART receiver FIFO
— nCTS (input) from modem controls UART transmitter
•
Fully programmable serial-interface:
— 5-, 6-, 7-, or 8-bit characters
— Even, odd, and no parity detection
— 1, 1.5, or 2 stop bit generation
— Baud rate generation up to 921 Kbps
— False start bit detection.
•
64-byte transmit FIFO
•
64-byte receive FIFO
•
Complete status reporting capability
•
Ability to generate and detect line breaks
•
Internal diagnostic capabilities that include:
— Loopback controls for communications link fault isolation
— Break, parity, and framing error simulation
•
Fully prioritized interrupt system controls
•
Separate DMA requests for transmit and receive data services
•
Slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA)
standard