Intel PXA255, Developer'S Manual

Page: 144 / 600

4-40 Intel® PXA255 Processor Developer’s Manual
System Integration Unit
comparator contains PWM_PERVALn[PV] and clears the PWM_OUT signal low when
PWM_PERVALn[PV] + 1 and the 10-bit up counter are equal. Both PWM_PERVALn[PV] and
PWM_DUTYn[DCYCLE] are 10 bit fields.
Note: Take care to ensure that the value of the PWM_PERVAL n register remains larger than
PWM_DUTY n register. In the case where PWM_PERVAL n is less than PWM_DUTY n the output
maintains a high state.
4.5.1.2 Reset Sequence
A system reset results in no pulse width modulated signal. During system reset the PWM_CTRL n
and PWM_DUTY n registers are reset to 0x0 and the PWM_PERVAL n register is set to 0x004.
This sets the PWM_OUT n pin low with a zero duty cycle. The six bit down-counter is reset to 0x0
and thus the 3.68 MHz input clock directly drives the 10 bit up-counter. The PWM_OUT n pin
remains reset low until the PWM_DUTYn register is programmed with a non zero value.
A basic pulse width waveform is shown in Figure 4-4 .
4.5.1.3 Power Management Requirements
Each PWM may be disabled through a pair of clock enable bits (see Section 3.6.2, “Clock Enable
Register (CKEN)” on page 3-36 ). If the clock is disabled, the unit shuts down in one of two ways:
•
Abrupt – the PWM stops immediately.
•
Graceful
–
the PWM completes the current duty cycle before stopping.
Shutdown is selected by PWM_CTRL[PWM_SD] and described in Section 4.5.2.1 .
4.5.2 Register Descriptions
The following paragraphs provide register descriptions for the Pulse Width Modulator.
4.5.2.1 PWM Control Registers (PWM_CTRL n )
The PWM_CTRL n, shown in Table 4-46 , contains two fields:
•
PRESCALE – The PRESCALE field contains the 6-bit prescale counter load value. This field
allows the 3.6864 MHz input clock PSCLK_PWM n , to be divided by values between 1
(PWM_CTL[PRESCALE] = 0) and 64 (PWM_CTL[PRESCALE] = 63).
Note: The value of the divisor is one greater than the value programmed into the PRESCALE field.
•
PWM_SD – PWM n can shut down in one of two ways, gracefully or abruptly, depending on
the setting of PWM_CTRL n [PWM_SD]. If gracefully is chosen, then the duty cycle counter
completes its count before PWM n is shut down. If abruptly is chosen, then the prescale
counter and the duty cycle counter are reset to the reload values in their associated registers
and PWM
n is immediately shut down.
Note: During abrupt shut down the PWM_OUT n signal may be delayed by up to one PSCLK_PWM n
clock period.