XC886/888CLM
Serial Interfaces
User’s Manual
12-14
V1.3, 2010-02
Serial Interfaces, V 1.0
Fractional Divider
The input clock
f
DIV
to the 8-bit fractional divider is scaled either by a factor of 1/n, or
n/256 to generate an output clock
f
MOD
for the baud rate timer. The fractional divider has
two operating modes:
•
Fractional divider mode
•
Normal divider mode
Fractional Divider Mode
The fractional divider mode is selected by clearing bit FDM in register FDCON to 0. Once
the fractional divider is enabled (FDEN = 1), the output clock
f
MOD
of the fractional divider
is derived from scaling its input clock
f
DIV
by a factor of n/256, where n is defined by bit
field STEP in register FDSTEP and can take any value from 0 to 255.
In fractional divider mode, the output clock pulse f
MOD
is dependent on the result of the
addition FDRES. FDSTEP.STEP; if the addition leads to an overflow over
FF
H
, a pulse is generated for f
MOD
.
The average output frequency in fractional divider mode is derived as follows:
(12.4)
Table 12-3
Deviation Error for UART with Fractional Divider enabled
f
PCLK
Prescaling Factor
(2
BRPRE
)
Reload Value
(BR 1)
STEP
Deviation
Error
26.67 MHz
1
10 (A
H
)
177 (B1
H
)
+0.03 %
24 MHz
1
10 (A
H
)
197 (C5
H
)
+0.20 %
16 MHz
1
8 (8
H
)
236 (EC
H
)
+0.03 %
13.33 MHz
1
7 (7
H
)
248 (F8
H
)
+0.11 %
12 MHz
1
6 (6
H
)
236 (EC
H
)
+0.03 %
8 MHz
1
4 (4
H
)
236 (EC
H
)
+0.03 %
6.67 MHz
1
3 (3
H
)
212 (D4
H
)
-0.16 %
6 MHz
1
3 (3
H
)
236 (EC
H
)
+0.03 %
256
STEP
DIV
f
MOD
f
x
=
255
-
0
TEP
where
=
S
*
