XC886/888CLM
Processor Architecture
User’s Manual
2-9
V1.3, 2010-02
Processor Architecture, V 1.0
Note: The XC886/888 CPU fetches the opcode of the next instruction while executing
the current instruction.
provides a reference for the number of clock cycles required by each
instruction. The first value applies to fetching operand(s) and opcode from fast program
memory (e.g., Boot ROM and XRAM) without wait state. The second value applies to
fetching operand(s) and opcode from slow program memory (e.g., Flash) with one wait
state inserted. The instruction time for the standard 8051 processor is provided in the last
column for performance comparison with the XC886/888 CPU. Even with one wait state
inserted for each byte of operand/opcode fetched, the XC886/888 CPU executes
instructions faster than the standard 8051 processor by a factor of between two (e.g., 2-
byte, 1-cycle instructions) to six (e.g., 1-byte, 4-cycle instructions).
Table 2-1
CPU Instruction Timing
Mnemonic
Hex Code Bytes
Number of
f
CCLK
Cycles
XC886/888
8051
no ws
1 ws
1 ws (with
parallel read)
1)
ARITHMETIC
ADD A,Rn
28-2F
1
2
4
2 or 4
12
ADD A,dir
25
2
2
6
4
12
ADD A,@Ri
26-27
1
2
4
2 or 4
12
ADD A,#data
24
2
2
6
4
12
ADDC A,Rn
38-3F
1
2
4
2 or 4
12
ADDC A,dir
35
2
2
6
4
12
ADDC A,@Ri
36-37
1
2
4
2 or 4
12
ADDC A,#data
34
2
2
6
4
12
SUBB A,Rn
98-9F
1
2
4
2 or 4
12
SUBB A,dir
95
2
2
6
4
12
SUBB A,@Ri
96-97
1
2
4
2 or 4
12
SUBB A,#data
94
2
2
6
4
12
INC A
04
1
2
4
2 or 4
12
INC Rn
08-0F
1
2
4
2 or 4
12
INC dir
05
2
2
6
4
12
INC @Ri
06-07
1
2
4
2 or 4
12
DEC A
14
1
2
4
2 or 4
12
*
