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Infineon XC886CLM, User Manual

The Infineon XC886CLM is a powerful microcontroller with exceptional performance and reliability. Users can easily understand its features and functionalities by downloading the free user manual from manualshive.com. This manual provides detailed instructions on how to maximize the potential of this advanced product.

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XC886/888CLM

Serial Interfaces

 

User’s Manual

12-5

V1.3, 2010-02

Serial Interfaces, V 1.0

 

12.1.1.3

Mode 2, 9-Bit UART, Fixed Baud Rate

In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a
programmable 9th bit and a stop bit (1) are transmitted on TXD or received on RXD. The
9th bit for transmission is taken from TB8 (SCON.3) while for reception, the 9th bit
received is placed in RB8 (SCON.2).

The transmission cycle is activated by a write to SBUF. The data is transferred to the
transmit register and TB8 is copied into the 9th bit position. At phase 1 of the machine
cycle following the next rollover in the divide-by-16 counter, the start bit is copied to TXD
and data is activated one bit time later. One bit time after the data is activated, the data
starts shifting right. For the first shift, a stop bit (1) is shifted in from the left and for
subsequent shifts, zeros are shifted in. When the TB8 bit gets to the output position, the
control block executes one last shift and sets the TI bit.

Reception is started by a high to low transition on RXD (sampled at 16 times the baud
rate). The divide-by-16 counter is then reset and 1111 1111

B

 is written to the receive

register. If a valid start bit (0) is then detected (based on two out of three samples), it is
shifted into the register followed by 8 data bits. If the transition is not followed by a valid
start bit, the controller goes back to looking for a high to low transition on RXD. When the
start bit reaches the leftmost position, the control block executes one last shift, then
loads SBUF with the 8 data bits, loads RB8 (SCON.2) with the 9th data bit, and sets the
RI bit, provided RI = 0, and either SM2 = 0 (see 

Section 12.1.2

) or the 9th bit = 1. If none

of these conditions is met, the received byte is lost.

The baud rate for the transfer is either 

f

PCLK

/64 or 

f

PCLK

/32 for UART module, depending

on the setting of the top bit (SMOD) of the PCON (Power Control) register, which acts as
a Double Baud Rate selector. For UART1 module, the baud rate is fixed at 

f

PCLK

/64.

12.1.1.4

Mode 3, 9-Bit UART, Variable Baud Rate

Mode 3 is the same as mode 2 in all respects except that the baud rate is variable.

In all modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in the modes by the incoming start bit if REN = 1.

The serial interface also provides interrupt requests when transmission or reception of
the frames has been completed. The corresponding interrupt request flags are TI or RI,
respectively. If the serial interrupt is not used (i.e., serial interrupt not enabled), TI and
RI can also be used for polling the serial interface.

The associated timings for transmit/receive in modes 2 and 3 are illustrated
in

Figure 12-2

.

*

Summary of Contents for XC886CLM

Page 1: ...User s Manual V1 3 2010 02 Microcontrollers 8 Bit XC886 888CLM 8 Bit Single Chip Microcontroller...

Page 2: ...y terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For inform...

Page 3: ...User s Manual V1 3 2010 02 Microcontrollers 8 Bit XC886 888CLM 8 Bit Single Chip Microcontroller...

Page 4: ...g integer is removed since normalization always involves a 32 bit variable 12 31 Direction of RXD slave signal in Figure 12 11 is corrected 14 3 Handling of T12 period register is elaborated 16 6 Conv...

Page 5: ...er Control PCON 2 6 2 3 Instruction Timing 2 6 3 Memory Organization 3 1 3 1 Compatibility between Flash and ROM devices 3 3 3 2 Program Memory 3 4 3 3 Data Memory 3 4 3 3 1 Internal Data Memory 3 4 3...

Page 6: ...rization 4 3 4 3 Parallel Read Access of P Flash 4 5 4 4 Wordline Address 4 6 4 5 Operating Modes 4 11 4 6 Error Detection and Correction 4 12 4 6 1 Flash Error Address Register 4 13 4 7 In System Pro...

Page 7: ...10 6 2 Register Map 6 11 6 3 Port 0 6 13 6 3 1 Functions 6 13 6 3 1 1 Register Description 6 17 6 4 Port 1 6 20 6 4 1 Functions 6 20 6 4 2 Register Description 6 24 6 5 Port 2 6 27 6 5 1 Functions 6...

Page 8: ...egister Description 8 5 9 Watchdog Timer 9 1 9 1 Functional Description 9 2 9 1 1 Module Suspend Control 9 4 9 2 Register Map 9 5 9 3 Register Description 9 5 10 Multiplication Division Unit 10 1 10 1...

Page 9: ...rfaces 12 1 12 1 UART 12 2 12 1 1 UART Modes 12 2 12 1 1 1 Mode 0 8 Bit Shift Register Fixed Baud Rate 12 2 12 1 1 2 Mode 1 8 Bit UART Variable Baud Rate 12 3 12 1 1 3 Mode 2 9 Bit UART Fixed Baud Rat...

Page 10: ...ations 13 2 13 1 2 Timer Modes 13 3 13 1 2 1 Mode 0 13 4 13 1 2 2 Mode 1 13 5 13 1 2 3 Mode 2 13 6 13 1 2 4 Mode 3 13 7 13 1 3 Port Control 13 8 13 1 4 Register Map 13 9 13 1 5 Register Description 13...

Page 11: ...7 Interrupt Generation 14 25 14 1 8 Low Power Mode 14 26 14 1 9 Module Suspend Control 14 27 14 1 10 Port Connection 14 28 14 2 Register Map 14 32 14 3 Register Description 14 35 14 3 1 System Registe...

Page 12: ...nsmission 15 30 15 1 9 Message Object Functionality 15 33 15 1 9 1 Standard Message Object 15 33 15 1 9 2 Single Data Transfer Mode 15 33 15 1 9 3 Single Transmit Trial 15 33 15 1 9 4 Message Object F...

Page 13: ...24 16 4 8 2 Channel Interrupts 16 25 16 4 9 External Trigger Inputs 16 27 16 5 ADC Module Initialization Sequence 16 28 16 6 Register Map 16 30 16 7 Register Description 16 33 16 7 1 General Function...

Page 14: ...4 The Activation of Modes 1 3 and F 18 12 18 1 2 5 The Activation of Mode 4 18 12 18 1 2 6 The Activation of Mode 6 18 14 18 1 2 7 The Activation of Mode A 18 15 18 1 3 Bootstrap Loader via LIN 18 16...

Page 15: ...AP allowing user program to modify Flash contents during program execution In System Programming ISP is available through the Boot ROM based BootStrap Loader BSL enabling convenient programming and er...

Page 16: ...and TQFP 64 which is denoted by XC888 Table 1 1 Device Configuration Device Name CAN Module LIN BSL Support MDU Module XC886 888 No No No XC886 888C Yes No No XC886 888CM Yes No Yes XC886 888LM No Yes...

Page 17: ...nless stated otherwise Table 1 2 Device Profile Sales Type Device Type Program Memory Kbytes Power Supply V Temp erature C Quality Profile SAA XC886 8FFA 5V Flash 32 5 0 40 to 140 Automotive SAA XC886...

Page 18: ...ly On chip OSC and PLL for clock generation PLL loss of lock detection Power saving modes slow down mode idle mode power down mode with wake up capability via RXD or EXINT0 clock gating control to eac...

Page 19: ...y in PG TQFP 48 pin package with 5 0 V power supply voltage ADC Port 0 Port 1 Port 2 Port 3 UART1 CORDIC SSC MDU Timer 2 12 Kbyte Boot ROM1 256 byte RAM 64 byte monitor RAM 1 5 Kbyte XRAM 24 32 Kbyte...

Page 20: ...own in Figure 1 4 Figure 1 3 XC886 Pin Configuration PG TQFP 48 Package top view XC886 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 24 23 22 21 20 19 18 17 16 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 37 38...

Page 21: ...40 39 38 37 36 35 34 33 64 63 62 53 54 55 56 57 58 59 60 61 49 50 51 52 RESET P3 5 P3 4 P2 2 VDDP P1 3 P1 4 P5 0 P4 2 P4 1 P4 0 P1 2 VSSP P5 1 P2 0 P0 3 P0 4 P0 5 P1 6 P1 7 P2 1 V SSC V DDC XTAL2 XTA...

Page 22: ...n 8 bit bidirectional general purpose I O port It can be used as alternate functions for the JTAG CCU6 UART UART1 Timer 2 Timer 21 MultiCAN and SSC P0 0 11 17 Hi Z TCK_0 T12HR_1 CC61_1 CLKOUT_0 RXDO_1...

Page 23: ...Receive Input Input Output of Capture Compare channel 2 UART1 Transmit Data Output Clock Output P0 5 2 1 Hi Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62_1 SSC Master Receive Input Slave Transmit Output Ext...

Page 24: ...ut JTAG Serial Data Output UART Transmit Data Output Clock Output MultiCAN Node 0 Transmitter Output P1 2 28 36 PU SCK_0 SSC Clock Input Output P1 3 29 37 PU MTSR_0 TXDC1_3 SSC Master Transmit Output...

Page 25: ...rnal Interrupt Input 6 MultiCAN Node 0 Receiver Input Timer 21 Input P1 7 9 11 PU CCPOS2_1 T13HR_0 T2_1 TXDC0_2 CCU6 Hall Input 2 CCU6 Timer 13 Hardware Run Input Timer 2 Input MultiCAN Node 0 Transmi...

Page 26: ...pare channel 1 Analog Input 0 P2 1 15 23 Hi Z CCPOS1_0 EXINT2_0 T13HR_2 TDI_1 CC62_3 AN1 CCU6 Hall Input 1 External Interrupt Input 2 CCU6 Timer 13 Hardware Run Input JTAG Serial Data Input Input of C...

Page 27: ...Output Clock Output P3 2 37 49 Hi Z CCPOS2_2 RXDC1_1 RXD1_1 CC61_0 CCU6 Hall Input 2 MultiCAN Node 1 Receiver Input UART1 Receive Data Input Input Output of Capture Compare channel 1 P3 3 38 50 Hi Z...

Page 28: ...al 1 14 V1 3 2010 02 Introduction V 1 1 P3 7 34 42 Hi Z EXINT4 COUT63_0 External Interrupt Input 4 Output of Capture Compare channel 3 Table 1 3 Pin Definitions and Functions cont d Symbol Pin Number...

Page 29: ...EXINT6_1 T21_0 External Interrupt Input 6 Timer 21 Input P4 3 32 40 Hi Z EXF21_1 COUT63_2 Timer 21 External Flag Output Output of Capture Compare channel 3 P4 4 45 Hi Z CCPOS0_3 T0_0 CC61_4 CCU6 Hall...

Page 30: ...terrupt Input 2 P5 2 12 PU RXD_2 UART Receive Data Input P5 3 13 PU TXD_2 UART Transmit Data Output Clock Output P5 4 14 PU RXDO_2 UART Transmit Data Output P5 5 15 PU TDO_2 TXD1_2 JTAG Serial Data Ou...

Page 31: ...og modules All pins must be connected VSSP 18 42 26 54 I O Ground All pins must be connected VDDC 6 6 Core Supply Monitor 2 5 V VSSC 5 5 Core Supply Ground VAREF 24 32 ADC Reference Voltage VAGND 23 3...

Page 32: ...eated as needed The default radix is decimal Hexadecimal constants have a suffix with the subscript letter H e g C0H Binary constants have a suffix with the subscript letter B e g 11B When the extents...

Page 33: ...to preserve compatibility with future products Setting the bit fields to 1 may lead to unpredictable results Undefined Certain bit combinations in a bit field can be labeled Reserved indicating that...

Page 34: ...mming I O Input Output ISP In System Programming JTAG Joint Test Action Group LIN Local Interconnect Network MDU Multiplication Division Unit NMI Non Maskable Interrupt OCDS On Chip Debug Support PC P...

Page 35: ...akpoint support and read write access to the data memory program memory and Special Function Registers SFRs Features Two clocks per machine cycle architecture for memory access without wait state Wait...

Page 36: ...ND OR Exclusive OR complement and rotate right left or swap nibble left four Also included is a Boolean processor performing the bit operations such as set clear complement jump if set jump if not set...

Page 37: ...and POP instructions respectively Instructions that use the stack automatically pre increment or post decrement the stack pointer so that the stack pointer always points to the last byte written to th...

Page 38: ...are after each instruction to indicate an odd even number of one bits in the accumulator i e even parity F1 1 rw General Purpose Flag OV 2 rwh Overflow Flag Used by arithmetic instructions RS1 RS0 4 3...

Page 39: ...er The instruction uses the opcode A5H which is the same as the software break instruction TRAP see Table 2 1 Register bit EO TRAP_EN is used to select the instruction executed by the opcode A5H When...

Page 40: ...machine cycle 2 Memory accesses take place during one or both phases of the machine cycle SFR writes only occur at the end of P2 An instruction takes one two or four machine cycles to execute Register...

Page 41: ...agram shows the instruction being executed within one machine cycle since the second byte C1P1 and the opcode C1P2 are fetched from a memory without wait state The second diagram shows the correspondi...

Page 42: ...88 CPU pipeline fCCLK C1P1 C1P2 Read next opcode without wait state C1P1 C1P2 a 1 byte 1 cycle instruction e g INC A WAIT WAIT Read next opcode one wait state C1P1 C1P2 Read next opcode without wait s...

Page 43: ...PU Even with one wait state inserted for each byte of operand opcode fetched the XC886 888 CPU executes instructions faster than the standard 8051 processor by a factor of between two e g 2 byte 1 cyc...

Page 44: ...2 ANL dir A 52 2 2 6 4 12 ANL dir data 53 3 4 10 6 or 8 24 ORL A Rn 48 4F 1 2 4 2 or 4 12 ORL A dir 45 2 2 6 4 12 ORL A Ri 46 47 1 2 4 2 or 4 12 ORL A data 44 2 2 6 4 12 ORL dir A 42 2 2 6 4 12 ORL di...

Page 45: ...MOV Rn data 78 7F 2 2 6 4 12 MOV dir A F5 2 2 6 4 12 MOV dir Rn 88 8F 2 4 8 6 24 MOV dir dir 85 3 4 10 6 or 8 24 MOV dir Ri 86 87 2 4 8 6 24 MOV dir data 75 3 4 10 6 or 8 24 MOV Ri A F6 F7 1 2 4 2 or...

Page 46: ...12 SETB bit D2 2 2 6 4 12 CPL C B3 1 2 4 2 or 4 12 CPL bit B2 2 2 6 4 12 ANL C bit 82 2 4 8 6 24 ANL C bit B0 2 4 8 6 24 ORL C bit 72 2 4 8 6 24 ORL C bit A0 2 4 8 6 24 MOV C bit A2 2 2 6 4 12 MOV bi...

Page 47: ...DF 2 4 8 6 or 8 24 DJNZ dir rel D5 3 4 10 6 or 8 24 MISCELLANEOUS NOP 00 1 2 4 2 or 4 12 ADDITIONAL INSTRUCTIONS MOVC DPTR A A5 1 4 4 4 or 6 TRAP A5 1 2 1 With parallel read the number of clock cycle...

Page 48: ...ry address spaces of the 32 Kbyte Flash devices For the 24 Kbyte Flash devices the shaded banks are not available Figure 3 1 Memory Map of XC886 888 Flash Device 0000H 2000H 4000H 6000H F000H C000H F6...

Page 49: ...ot be used to store user code or data Therefore even though the ROM device contains either a 24 Kbyte or 32 Kbyte ROM the maximum size of code that can be placed in the ROM is the given size less four...

Page 50: ...es address space from 7FFCH to 7FFFH in the Flash device For example if the Flash device is used as a prototype to develop the 32 Kbyte less four bytes program code later stored in 32 Kbyte ROM memory...

Page 51: ...the clock Hence there is no concept of internal or external program memory as all code is fetched from a single program memory interface 3 3 Data Memory The data memory space consists of an internal...

Page 52: ...he DPTR register is used for 16 bit addressing either register R0 or R1 is used to form the 8 bit address The upper byte of the XRAM address during execution of the 8 bit accesses is defined by the va...

Page 53: ...ed to implement a second layer of read out protection as well as to enable program and erase protection Flash hardware protection is available only for Flash devices and comes in two modes Mode 0 Only...

Page 54: ...extra step serves to prevent inadvertent destruction of the D Flash contents Parallel erase of the D Flash banks is disallowed in Flash protection mode 0 Two D Flash erase operations are needed to er...

Page 55: ...ce Here entering BSL mode 6 will result in a protection error Note If ROM read out protection is enabled only read instructions in the ROM memory can target the ROM contents Table 3 2 User Programmabl...

Page 56: ...the erase of a D Flash bank This bit has no effect if the Flash hardware protection is not enabled or protection mode 1 is enabled MISC_CON Miscellaneous Control Register Reset Value 00H 7 6 5 4 3 2...

Page 57: ...Address extension is performed at the system level by mapping The SFR area is extended into two portions the standard non mapped SFR area and the mapped SFR area Each portion supports the same addres...

Page 58: ...ganization V 1 2 Figure 3 4 Address Extension by Mapping Module 1 SFRs SYSCON0 RMAP SFR Data to from CPU rw Standard Area RMAP 0 80H FFH 80H FFH Direct Internal Data Memory Address Mapped Area RMAP 1...

Page 59: ...d be cleared set using ANL or ORL instructions SYSCON0 System Control Register 0 Reset Value 04H 7 6 5 4 3 2 1 0 0 IMODE 0 1 0 RMAP r rw r r r rw Field Bits Type Description RMAP 0 rw Special Function...

Page 60: ...rectly controlled by the CPU instruction itself but is derived from bit field PAGE in the module page register MOD_PAGE Hence the bit field PAGE must be programmed before accessing the SFRs of the tar...

Page 61: ...tion can Save the contents of PAGE in STx before overwriting with the new value this is done at the beginning of the interrupt routine to save the current page setting and program the new page number...

Page 62: ...en the value indicates the new page When read the value indicates the currently active page STNR 5 4 w Storage Number This number indicates which storage bit field is the target of the operation defin...

Page 63: ...ctly written 10 New page programming with automatic page saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field ST...

Page 64: ...information SCU_PAGE Page Register for System Control Reset Value 00H 7 6 5 4 3 2 1 0 OP STNR 0 PAGE w w r rw Field Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the ne...

Page 65: ...saving The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR 11 Automatic restore page action The...

Page 66: ...ss password is written again before the end of 32 CCLK cycles there will be a recount of 32 CCLK cycles The protected bits include the N and K Divider bits NDIV and KDIV the Watchdog Timer enable bit...

Page 67: ...anization V 1 2 PASS 7 3 wh Password bits The Bit Protection Scheme only recognizes three patterns 11000BEnables writing of the bit field MODE 10011BOpens access to writing of all protected bits 10101...

Page 68: ...0H Data Pointer Register High Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 Type rw rw rw rw rw rw rw rw 87H PCON Reset 00H Power Control Register Bit Field SMOD 0 GF1 GF0 0 IDLE Type rw r rw rw r...

Page 69: ...ield ECCIP 3 ECCIP 2 ECCIP 1 ECCIP 0 EXM EX2 ESSC EADC Type rw rw rw rw rw rw rw rw F0H B Reset 00H B Register Bit Field B7 B6 B5 B4 B3 B2 B1 B0 Type rw rw rw rw rw rw rw rw F8H IP1 Reset 00H Interrup...

Page 70: ...Reset 00H MDU Result Register 4 Bit Field DATA Type rh B7H MD5 Reset 00H MDU Operand Register 5 Bit Field DATA Type rw B7H MR5 Reset 00H MDU Result Register 5 Bit Field DATA Type rh Table 3 5 CORDIC R...

Page 71: ...eral Input Select Register Bit Field 0 URRIS H JTAGT DIS JTAGT CKS EXINT 2IS EXINT 1IS EXINT 0IS URRIS Type r rw rw rw rw rw rw rw B4H IRCON0 Reset 00H Interrupt Request Register 0 Bit Field 0 EXINT 6...

Page 72: ...ty Register Bit Field PRODID VERID Type r r B4H PMCON0 Reset 00H Power Mode Control Register 0 Bit Field 0 WDT RST WKRS WK SEL SD PD WS Type r rwh rwh rw rw rwh rw B5H PMCON1 Reset 00H Power Mode Cont...

Page 73: ...Reset 00H Peripheral Input Select Register 1 Bit Field EXINT 6IS 0 UR1RIS T21EX IS JTAGT DIS1 JTAGT CKS1 Type rw r rw rw rw rw BAH MODPISEL2 Reset 00H Peripheral Input Select Register 2 Bit Field 0 T2...

Page 74: ...R Reset 00H P1 Direction Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_DATA Reset 00H P5 Data Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 9...

Page 75: ...ld P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B0H P3_PUDSEL Reset BFH P3 Pull Up Pull Down Select Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw B1H P3_PUDEN Reset 4...

Page 76: ...P1 P0 Type rw rw rw rw rw rw rw rw 90H P1_OD Reset 00H P1 Open Drain Control Register Bit Field P7 P6 P5 P4 P3 P2 P1 P0 Type rw rw rw rw rw rw rw rw 92H P5_OD Reset 00H P5 Open Drain Control Register...

Page 77: ...ld 0 LCC 0 RESRSEL Type r rw r rw CFH ADC_CHCTR5 Reset 00H Channel Control Register 5 Bit Field 0 LCC 0 RESRSEL Type r rw r rw D2H ADC_CHCTR6 Reset 00H Channel Control Register 6 Bit Field 0 LCC 0 RES...

Page 78: ...rh D3H ADC_RESRA3H Reset 00H Result Register 3 View A High Bit Field RESULT Type rh RMAP 0 PAGE 4 CAH ADC_RCR0 Reset 00H Result Control Register 0 Bit Field VFCT R WFR 0 IEN 0 DRCT R Type rw rw r rw r...

Page 79: ...de Pointer Register Bit Field EVINP 7 EVINP 6 EVINP 5 EVINP 4 0 EVINP 1 EVINP 0 Type rw rw rw rw r rw rw RMAP 0 PAGE 6 CAH ADC_CRCR1 Reset 00H Conversion Request Control Register 1 Bit Field CH7 CH6 C...

Page 80: ...r 2 Reload Capture Register Low Bit Field RC2 Type rwh C3H T2_RC2H Reset 00H Timer 2 Reload Capture Register High Bit Field RC2 Type rwh C4H T2_T2L Reset 00H Timer 2 Register Low Bit Field THL2 Type r...

Page 81: ...Control Register 4 High Bit Field T13 STD T13 STR 0 T13 RES T13R S T13R R Type w w r w w w 9EH CCU6_MCMOUTSL Reset 00H Multi Channel Mode Output Shadow Register Low Bit Field STRM CM 0 MCMPS Type w r...

Page 82: ...t 00H Capture Compare Register for Channel CC63 High Bit Field CC63VH Type rh 9CH CCU6_T12PRL Reset 00H Timer T12 Period Register Low Bit Field T12PVL Type rwh 9DH CCU6_T12PRH Reset 00H Timer T12 Peri...

Page 83: ...Type rw rw rw rw rw rw rw rw 9DH CCU6_IENH Reset 00H Capture Compare Interrupt Enable Register High Bit Field EN STR EN IDLE EN WHE EN CHE 0 EN TRPF ENT1 3PM ENT1 3CM Type rw rw rw rw r rw rw rw 9EH...

Page 84: ...t 00H Capture Compare Interrupt Status Register Low Bit Field T12 PM T12 OM ICC62 F ICC62 R ICC61 F ICC61 R ICC60 F ICC60 R Type rh rh rh rh rh rh rh rh 9DH CCU6_ISH Reset 00H Capture Compare Interrup...

Page 85: ...ew Addr Register Name Bit 7 6 5 4 3 2 1 0 RMAP 1 C8H SCON Reset 00H Serial Channel Control Register Bit Field SM0 SM1 SM2 REN TB8 RB8 TI RI Type rw rw rw rw rw rwh rwh rwh C9H SBUF Reset 00H Serial Da...

Page 86: ...N BEN PEN REN TEN Type rw rw r rw rw rw rw rw ABH SSC_CONH Reset 00H Control Register High Operating Mode Bit Field EN MS 0 BSY BE PE RE TE Type rw rw r rh rwh rwh rwh rwh ACH SSC_TBL Reset 00H Transm...

Page 87: ...eld MEXIT _P MEXIT 0 MSTE P MRAM S_P MRAM S TRF RRF Type w rwh r rw w rwh rh rh F2H MMSR Reset 00H Monitor Mode Status Register Bit Field MBCA M MBCIN EXBF SWBF HWB3 F HWB2 F HWB1 F HWB0 F Type rw rwh...

Page 88: ...e 0000H 2FFFH and C000H EFFFH will be mapped to only C000H EFFFH Also the remaining program memory blocks XRAM P Flash and D Flash are enabled After the active memory map switch the remaining Boot ROM...

Page 89: ...ate Flash programming Note User should always program a non zero value to program memory address 0000H to avoid entering BSL mode unintentionally 3 6 2 Bootstrap Loader Mode If MBC TMS P0 0 0 0 x the...

Page 90: ...cuted and the debugging process may be started During the OCDS mode the lowest 64 bytes 00H 3FH in the internal data memory address range may be alternatively mapped to the 64 byte monitor RAM or the...

Page 91: ...mming or erasing voltage The sectorization of the Flash memory allows each sector to be erased independently Features In System Programming ISP via UART In Application Programming IAP Error Correction...

Page 92: ...ometimes referred to as P Flash bank pair P Flash banks 0 and 1 constitute P Flash bank pair 0 P Flash banks 2 and 3 constitute P Flash bank pair 1 and P Flash banks 4 and 5 constitute P Flash bank pa...

Page 93: ...bank s contents that are intended to be used as data All ROM devices in the XC886 888 product family offer a 4 Kbyte D Flash bank mapped to the address space A000H AFFFH 4 2 Flash Bank Sectorization...

Page 94: ...re 4 3 P Flash Bank Pair Sectorization Sector Partitioning in D Flash Two 1 Kbyte sectors Two 512 byte sectors Two 256 byte sectors Four 128 byte sectors The internal structure of each Flash bank repr...

Page 95: ...the emulated EEPROM size significantly increases the Flash endurance To speed up data search the RAM can be used to contain the pointer to the valid data set 4 3 Parallel Read Access of P Flash To enh...

Page 96: ...r 0 P Flash Pair 1 P Flash Pair 2 Sector 0 WL 0 119 3 75 KByte x 2 Sector 1 WL 120 123 128 byte x 2 Sector 2 WL 124 127 128 byte x 2 Sector 0 WL 0 119 3 75 KByte x 2 Sector 1 WL 120 123 128 byte x 2 S...

Page 97: ...11 2 56 b yte WL Address Secto r 6 W L 112 11 5 12 8 byte S ecto r 7 W L 1 16 119 12 8 byte S ector 8 W L 1 20 123 128 b yte Se ctor 9 W L 1 24 1 27 1 28 b yte 7000H 7001H 7002H 701FH 7020H 7021H 702...

Page 98: ...11 2 56 b yte WL Address Secto r 6 W L 112 11 5 12 8 byte S ecto r 7 W L 1 16 119 12 8 byte S ector 8 W L 1 20 123 128 b yte Se ctor 9 W L 1 24 1 27 1 28 b yte B000H B001H B002H B01FH B020H B021H B022...

Page 99: ...is necessary to fill the IRAM with the number of bytes of data as defined by the program width otherwise the previous values stored in the write buffers will remain and be programmed into the WL For t...

Page 100: ...Program 0000 0000 H 0000 0000 H 32 bytes 1 WL 1111 1111H 0000 0000 H 16 bytes 16 bytes 0000 0000 H 1111 1111 H Flash memory cells 32 byte write buffers 1111 0000 H 1111 1111 H 0000 0000H 1111 0000 H...

Page 101: ...lash bank are enforced by its dedicated state machine to ensure the correct sequence of Flash mode transition This avoids inadvertent destruction of the Flash contents with a reasonably low software o...

Page 102: ...ty to Detect and correct all 1 bit errors Detect all 2 bit errors but cannot correct No distinction is made between a corrected 1 bit error result is valid and an uncorrected 2 bit error result is inv...

Page 103: ...t Flash address at which the ECC error occurs FEAL Flash Error Address Register Low Reset Value 00H 7 6 5 4 3 2 1 0 ECCERRADDR rh Field Bits Type Description ECCERRADDR 7 0 rh ECC Error Address Value...

Page 104: ...le The BSL mode is selected if the latched values of the MBC and TMS pins are 0 after power on or hardware reset The BSL routine will first perform an automatic synchronization with the transfer speed...

Page 105: ...the completion of the program or erase operation A manual check on the Flash data is necessary to determine if the programming or erasing was successful via using the MOVC instruction to read out the...

Page 106: ...ash bank write buffers exit the subroutine and then return to the user program code see Table 4 1 User program code will continue execution from where it last stopped until the Flash NMI event is gene...

Page 107: ...ode User program code will continue execution from where it last stopped until the Flash NMI event is generated bit FNMIFLASH in register NMISR is set and if enabled via NMIFLASH an NMI to the CPU is...

Page 108: ...two consecutive aborted erase as data in relevant sector s is corrupted R6 Select sector s to be erased for P Flash Bank Pair 1 LSB represents sector 0 bit 2 represents sector 2 R7 Select sector s to...

Page 109: ...cannot be aborted A successful abort action is indicated by a Flash NMI event bit FNMIFLASH in register NMISR is set and if enabled via NMICON NMIFLASH an NMI to the CPU is triggered to enter the Fla...

Page 110: ...the parallel read feature is also provided Table 4 4 Flash Bank Read Status Subroutine Subroutine DFF0H FLASH_READ_STATUS Input ACC Select desired Flash bank for ready to read status 00H P Flash Bank...

Page 111: ...the particular device variant Table 4 6 Get Chip Information Subroutine Subroutine DFE1H GET_CHIP_INFO Input ACC 00H Chip Identification Number Others Reserved R1 of Current Register Bank IRAM start...

Page 112: ...vector Timer 2 Timer 21 CORDIC MDU UART1 MultiCAN ADC CCU6 the Fractional Dividers and LIN share the other eight interrupt vectors Two of these interrupt vectors are also shared with External Interrup...

Page 113: ...d by hardware 000B H ET0 IEN0 1 TF0 TCON 5 Timer 0 Overflow 001B H ET1 IEN0 3 TF1 TCON 7 Timer 1 Overflow IP 1 IPH 1 IP 3 IPH 3 0023 H ES IEN0 4 IP 4 IPH 4 1 RI SCON 0 TI SCON 1 UART Transmit 0003 H E...

Page 114: ...IPH 5 P o l l i n g S e q u e n c e 0033 H EADC IEN1 0 IP1 0 IPH1 0 1 ADCSR0 IRCON1 3 ADC_0 ADC_1 ADCSR1 IRCON1 4 CANSRC1 IRCON1 5 MultiCAN_1 ET2 IEN0 5 1 TF2 T2_T2CON 7 EXF2 T2_T2CON 6 Timer 2 Overfl...

Page 115: ...e n c e 003B H ESSC IEN1 1 IP1 1 IPH1 1 1 TIR IRCON1 1 RIR IRCON1 2 EIR IRCON1 0 SSC_EIR SSC_TIR SSC_RIR IEN0 7 EA 0043 H IP1 2 IPH1 2 EXINT2 EXICON0 4 5 EXINT2 IRCON0 2 EINT2 EX2 IEN1 2 IRDY MDUSTAT...

Page 116: ...ghest Lowest Priority Level Bit addressable Request flag is cleared by hardware P o l l i n g S e q u e n c e EA 004B H EXM IEN1 3 IP1 3 IPH1 3 1 EXINT5 EXICON1 2 3 EXINT5 IRCON0 5 EINT5 EXINT3 EXICON...

Page 117: ...red by hardware EA 0053 H CCU6 interrupt node 0 IP1 4 IPH1 4 005B H IP1 5 IPH1 5 0063 H IP1 6 IPH1 6 006B H IP1 7 IPH1 7 ECCIP0 IEN1 4 ECCIP1 IEN1 5 ECCIP2 IEN1 6 ECCIP3 IEN1 7 CANSRC4 IRCON3 1 MultiC...

Page 118: ...quest flag is cleared by hardware 0073 H NMIWDT NMICON 0 WDT Overflow 1 Non Maskable Interrupt NMIPLL NMICON 1 PLL Loss of Lock NMIFLASH NMICON 2 NMIVDD NMICON 4 VDD Pre Warning NMIWDT NMIISR 0 NMIPLL...

Page 119: ...cept NMI to the core Resetting bit EA to 0 only masks the pending interrupt requests from the core but does not block the capture of incoming interrupt requests 5 1 1 Interrupt Structure 1 For interru...

Page 120: ...cture 2 If IMODE 1 an event generated by its corresponding interrupt source will set the status flag and in parallel if the event is enabled for interrupt generate a pending interrupt request to the c...

Page 121: ...n of EA bit and interrupt node enable bit is replaced by OR of all NMICON bits Therefore NMI node is non maskable when IMODE 1 whereas NMI pending interrupt request may be cleared by clearing all NMIC...

Page 122: ...888 interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are summarized in Table 5 1 Table 5 1 Interrupt Vector Addresses Interrupt Node Vector Address A...

Page 123: ...l Divider Overflow MDU 1 0 XINTR9 004BH External Interrupt 3 EXM External Interrupt 4 External Interrupt 5 External Interrupt 6 MultiCAN Node 3 XINTR10 0053H CCU6 INP0 ECCIP0 MultiCAN Node 4 XINTR11 0...

Page 124: ...es which request is serviced first Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 5 2 Table 5 2 Priority Structure within Int...

Page 125: ...is active but was not responded to for one of the conditions already mentioned or if the flag is no longer active at a later time when servicing the interrupt node the corresponding interrupt source w...

Page 126: ...time would be obtained if the request is blocked by one of the three previously listed conditions 1 If an interrupt of equal or higher priority is already in progress the additional wait time will de...

Page 127: ...n Figure 5 10 and Figure 5 11 Interrupt request sampled active 4 cycle current instruction MUL or DIV Interrupt request sampled LCALL 1st instruction at interrupt vector Interrupt request polled last...

Page 128: ...requests at once The NMI interrupt vector is shared by a number of sources each of which can be enabled or disabled individually via register NMICON After reset the enable bits in IEN0 IEN1 and NMICO...

Page 129: ...ed from the core 0 6 r Reserved Returns 0 if read should be written with 0 IEN1 Interrupt Enable Register 1 Reset Value 00H 7 6 5 4 3 2 1 0 ECCIP3 ECCIP2 ECCIP1 ECCIP0 EXM EX2 ESSC EADC rw rw rw rw rw...

Page 130: ...enabled NMICON NMI Control Register Reset Value 00H 7 6 5 4 3 2 1 0 0 NMIECC NMIVDDP NMIVDD NMIOCDS NMIFLAS H NMIPLL NMIWDT r rw rw rw rw rw rw rw Field Bits Type Description NMIWDT 0 rw Watchdog Tim...

Page 131: ...DP Prewarning NMI Enable 0 VDDP NMI is disabled 1 VDDP NMI is enabled Note When the external power supply is 3 3 V the user must disable NMIVDDP NMIECC 6 rw ECC NMI Enable 0 ECC NMI is disabled 1 ECC...

Page 132: ...low for at least one CCLK cycle to ensure that the transition is recognized If edge detection is bypassed for external interrupt 0 and external interrupt 1 the external source must hold the request p...

Page 133: ...5 4 3 2 1 0 0 EXINT6 EXINT5 EXINT4 r rw rw rw Field Bits Type Description EXINT4 1 0 rw External Interrupt 4 Trigger Select 00 Interrupt on falling edge 01 Interrupt on rising edge 10 Interrupt on bot...

Page 134: ...ternal Interrupt Input EXINT1_0 is selected 1 External Interrupt Input EXINT1_1 is selected EXINT2IS 3 rw External Interrupt 2 Input Select 0 External Interrupt Input EXINT2_0 is selected 1 External I...

Page 135: ...w rwh rw rwh rw rwh rw Field Bits Type Description IT0 0 rw External Interrupt 0 Level Edge Trigger Control Flag 0 Low level triggered external interrupt 0 is selected 1 Falling edge triggered externa...

Page 136: ...by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred These bits are set by corresponding active edge event i e falling rising both These f...

Page 137: ...t occurred 1 Interrupt event has occurred ADCSR0 3 rwh Interrupt Flag 0 for ADC This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has...

Page 138: ...has occurred CANSRC3 3 rwh Interrupt Flag 3 for MultiCAN This bit is set by hardware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred 0 7 5 3 1 r...

Page 139: ...dware and can only be cleared by software 0 Interrupt event has not occurred 1 Interrupt event has occurred 0 7 6 3 2 r Reserved Returns 0 if read should be written with 0 IRCON4 Interrupt Request Reg...

Page 140: ...rol Register Reset Value 00H 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 rwh rw rwh rw rwh rw rwh rw Field Bits Type Description IE0 1 rwh External Interrupt 0 Flag Set by hardware when external i...

Page 141: ...on RI 0 rwh Serial Interface Receiver Interrupt Flag Set by hardware if a serial data byte has been received Must be cleared by software TI 1 rwh Serial Interface Transmitter Interrupt Flag Set by har...

Page 142: ...ccurred 1 PLL loss of lock to the external crystal has occurred FNMIFLASH 2 rwh Flash NMI Flag 0 No Flash NMI has occurred 1 Flash NMI has occurred FNMIOCDS 3 rwh OCDS NMI Flag 0 No OCDS NMI has occur...

Page 143: ...NMI always has the highest priority above Level 3 it does not use the level selection shown in Table 5 3 Table 5 3 Interrupt Priority Level Selection IPH x IPH1 x IP x IP1 x Priority Level 0 0 Level...

Page 144: ...t Node XINTR4 PT2H 5 rw Priority Level High Bit for Interrupt Node XINTR5 0 7 6 r Reserved Returns 0 if read should be written with 0 IP1 Interrupt Priority 1 Register Reset Value 00H 7 6 5 4 3 2 1 0...

Page 145: ...PADCH 0 rw Priority Level High Bit for Interrupt Node XINTR6 PSSCH 1 rw Priority Level High Bit for Interrupt Node XINTR7 PX2H 2 rw Priority Level High Bit for Interrupt Node XINTR8 PXMH 3 rw Priority...

Page 146: ...EXF2 T2_T2CON Timer 21 Overflow TF2 T21_T2CON Timer 21 External Event EXF2 T21_T2CON LIN End of Syn Byte EOFSYN FDCON LIN Syn Byte Error ERRSYN FDCON UART Receive RI SCON UART Transmit TI SCON UART N...

Page 147: ...RC61 IRCON4 MultiCAN Interrupt 7 CANSRC71 IRCON4 CCU6 Node 0 Interrupt CCU6SR0 IRCON3 CCU6 Node 1 Interrupt CCU6SR1 IRCON3 CCU6 Node 2 Interrupt CCU6SR2 IRCON4 CCU6 Node 3 Interrupt CCU6SR3 IRCON4 Wat...

Page 148: ...the on chip peripherals When configured as an output the open drain mode can be selected Port P2 is an input only port providing general purpose input functions alternate input functions for the on ch...

Page 149: ...evice and can be read via the register Px_DATA In output mode the output driver is activated and drives the value supplied through the multiplexer to the port pin In the output driver each port line c...

Page 150: ...nd can be read via the register P2_DATA Each pin can also be programmed to activate an internal weak pull up or pull down device Register P2_PUDSEL selects whether a pull up or the pull down device is...

Page 151: ...l circuitry and Schmitt Trigger device for direct feed through to the ADC input channel Figure 6 2 General Structure of Input Port Px_DATA Data Register Internal Bus AltDataIn Px_PUDEN Pull up Pull do...

Page 152: ...Table 6 1 are implemented The availability and definition of registers specific to each port is defined in Section 6 3 to Section 6 8 This section provides only an overview of the different port regis...

Page 153: ...lts in register Px_DATA being updated with the active pull value Bit Px_DATA n can only be written if the corresponding pin is set to output Px_DIR n 1 and cannot be written if the corresponding pin i...

Page 154: ...only port pins register Px_DIR is used to enable or disable the input drivers Px_DIR Port x Direction Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 rw rw rw rw rw rw rw rw Field Bits Type Descript...

Page 155: ...aracteristics tristate high impedance with a weak pull up device high impedance with a weak pull down device and the following output characteristics push pull optional pull up pull down open drain wi...

Page 156: ...ype Description Pn n 0 7 n rw Pull Up Pull Down Select Port x Bit n 0 Pull down device is selected 1 Pull up device is selected Px_PUDEN Port x Pull Up Pull Down Enable Register 7 6 5 4 3 2 1 0 P7 P6...

Page 157: ...t lines This multiplexer can be controlled by the following registers Register Px_ALTSEL0 Register Px_ALTSEL1 Selection of alternate functions is defined in registers Px_ALTSEL0 and Px_ALTSEL1 Note Se...

Page 158: ...e 6 2 SFR Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 80H P0_DATA P0_PUDSEL P0_ALTSEL0 P0_OD 86H P0_DIR P0_PUDEN P0_ALTSEL1 90H P1_DATA P1_PUDSEL P1_ALTSEL0 P1_OD 91H P1_DIR P1_PUDE...

Page 159: ...y the contents of STx The value written to the bit positions of PAGE is ignored 00 ST0 is selected 01 ST1 is selected 10 ST2 is selected 11 ST3 is selected OP 7 6 w Operation 0X Manual page mode The v...

Page 160: ...0 Data Register P0_DIR Port 0 Direction Register P0_OD Port 0 Open Drain Control Register P0_PUDSEL Port 0 Pull Up Pull Down Select Register P0_PUDEN Port 0 Pull Up Pull Down Enable Register P0_ALTSE...

Page 161: ...EXF2_1 Timer 2 ALT2 COUT61_1 CCU6 ALT3 P0 2 Input GPI P0_DATA P2 ALT1 ALT2 CTRAP_2 CCU6 ALT3 Output GPO P0_DATA P2 ALT1 TDO_0 JTAG ALT2 TXD_1 UART ALT3 TXDC1_0 MultiCAN P0 3 Input GPI P0_DATA P3 ALT1...

Page 162: ...1 CCU6 ALT3 TXD1_0 UART1 P0 5 Input GPI P0_DATA P5 ALT1 MRST_1 SSC ALT2 EXINT0_0 External interrupt 0 ALT3 T2EX1_1 Timer 21 ALT4 RXD1_0 UART1 Output GPO P0_DATA P5 ALT1 MRST_1 SSC ALT2 COUT62_1 CCU6 A...

Page 163: ...Parallel Ports V 1 0 P0 7 Input GPI P0_DATA P7 ALT1 ALT2 ALT3 Output GPO P0_DATA P7 ALT1 CLKOUT_1 SCU ALT2 ALT3 1 Pin P0 6 is only available in XC888 Table 6 4 Port 0 Input Output Functions cont d Por...

Page 164: ...7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n 0 7 n rw Port 0 Pin n Data Value 0 Port 0 pin n data value 0 default 1 Port 0 pin n data value 1 P0_DIR...

Page 165: ...rw Port 0 Pin n Open Drain Mode 0 Normal mode output is actively driven for 0 and 1 states default 1 Open drain mode output is actively driven only for 0 state P0_PUDSEL Port 0 Pull Up Pull Down Sele...

Page 166: ...n Enable at Port 0 Bit n 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled default P0_ALTSELn n 0 1 Port 0 Alternate Select Register Reset Value 00H 7 6 5 4 3 2 1 0 P7...

Page 167: ...ll Name P1_DATA Port 1 Data Register P1_DIR Port 1 Direction Register P1_OD Port 1 Open Drain Control Register P1_PUDSEL Port 1 Pull Up Pull Down Select Register P1_PUDEN Port 1 Pull Up Pull Down Enab...

Page 168: ...P1 ALT1 TDO_1 JTAG ALT2 TXD_0 UART ALT3 TXDC0_0 MultiCAN P1 2 Input GPI P1_DATA P2 ALT1 SCK_0 SSC ALT2 ALT3 Output GPO P1_DATA P2 ALT1 SCK_0 SSC ALT2 ALT3 P1 3 Input GPI P1_DATA P3 ALT1 MTSR_0 SSC ALT...

Page 169: ...GPI P1_DATA P5 ALT1 CCPOS0_1 CCU6 ALT2 EXINT5 External interrupt 5 ALT3 T1_1 Timer 1 Output GPO P1_DATA P51 ALT1 EXF2_0 Timer 2 ALT2 RXDO_0 UART ALT3 P1 6 Input GPI P1_DATA P6 ALT1 CCPOS1_1 CCU6 ALT2...

Page 170: ...2 T13HR_0 CCU6 ALT3 T2_1 Timer 2 Output GPO P1_DATA P7 ALT1 ALT2 ALT3 TXDC0_2 MultiCAN 1 P1 5 can be used as a software Chip Select function for the SSC 2 P1 6 can be used as a software Chip Select fu...

Page 171: ...rw rw rw rw rw rw Field Bits Type Description Pn n 0 7 n rw Port 1 Pin n Data Value 0 Port 1 pin n data value 0 default 1 Port 1 pin n data value 1 P1_DIR Port 1 Direction Register Reset Value 00H 7 6...

Page 172: ...rw Port 1 Pin n Open Drain Mode 0 Normal mode output is actively driven for 0 and 1 states default 1 Open drain mode output is actively driven only for 0 state P1_PUDSEL Port 1 Pull Up Pull Down Sele...

Page 173: ...n Enable at Port 1 Bit n 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled default P1_ALTSELn n 0 1 Port 1 Alternate Select Register Reset Value 00H 7 6 5 4 3 2 1 0 P7...

Page 174: ...a Register P2_DIR Port 2 Direction Register P2_PUDSEL Port 2 Pull Up Pull Down Select Register P2_PUDEN Port 2 Pull Up Pull Down Enable Register Table 6 8 Port 2 Input Functions Port Pin Input Output...

Page 175: ...LT 4 ALT 5 CC60_3 CCU6 ANALOG AN2 ADC P2 3 Input GPI P2_DATA P3 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 ANALOG AN3 ADC P2 4 Input GPI P2_DATA P4 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 ANALOG AN4 ADC P2 5 Input GPI P2_DA...

Page 176: ...allel Ports V 1 0 P2 6 Input GPI P2_DATA P6 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 ANALOG AN6 ADC P2 7 Input GPI P2_DATA P7 ALT 1 ALT 2 ALT 3 ALT 4 ALT 5 ANALOG AN7 ADC Table 6 8 Port 2 Input Functions cont d...

Page 177: ...0 r r r r r r r r Field Bits Type Description Pn n 0 7 n r Port 2 Pin n Data Value 0 Port 2 pin n data value 0 default 1 Port 2 pin n data value 1 P2_DIR Port 2 Direction Register Reset Value 00H 7 6...

Page 178: ...Description Pn n 0 7 n rw Pull Up Pull Down Select Port 2 Bit n 0 Pull down device is selected 1 Pull up device is selected P2_PUDEN Port 2 Pull Up Pull Down Enable Register Reset Value 00H 7 6 5 4 3...

Page 179: ...e P3_DATA Port 3 Data Register P3_DIR Port 3 Direction Register P3_OD Port 3 Open Drain Control Register P3_PUDSEL Port 3 Pull Up Pull Down Select Register P3_PUDEN Port 3 Pull Up Pull Down Enable Reg...

Page 180: ...1_2 CCU6 ALT3 TXD1_1 UART1 P3 2 Input GPI P3_DATA P2 ALT1 CC61_0 CCU6 ALT2 CCPOS2_2 CCU6 ALT3 RXDC1_1 MultiCAN ALT4 RXD1_1 UART1 Output GPO P3_DATA P2 ALT1 CC61_0 CCU6 ALT2 ALT3 P3 3 Input GPI P3_DATA...

Page 181: ...ut GPO P3_DATA P4 ALT1 CC62_0 CCU6 ALT2 ALT3 P3 5 Input GPI P3_DATA P5 ALT1 ALT2 ALT3 Output GPO P3_DATA P5 ALT1 COUT62_0 CCU6 ALT2 EXF21_0 Timer 21 ALT3 TXDC0_1 MultiCAN P3 6 Input GPI P3_DATA P6 ALT...

Page 182: ...02 Parallel Ports V 1 0 P3 7 Input GPI P3_DATA P7 ALT1 ALT2 EXINT4 External interrupt 4 ALT3 Output GPO P3_DATA P7 ALT1 COUT63_0 CCU6 ALT2 ALT3 Table 6 10 Port 3 Input Output Functions cont d Port Pi...

Page 183: ...rw rw rw rw rw rw Field Bits Type Description Pn n 0 7 n rw Port 3 Pin n Data Value 0 Port 3 pin n data value 0 default 1 Port 3 pin n data value 1 P3_DIR Port 3 Direction Register Reset Value 00H 7 6...

Page 184: ...1 0 P7 P6 P5 P4 P3 P2 P1 P0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n 0 7 n rw Port 3 Pin n Open Drain Mode 0 Normal mode output is actively driven for 0 and 1 states default 1 Open dr...

Page 185: ...Down Enable at Port 3 Bit n 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled P3_ALTSELn n 0 1 Port 3 Alternate Select Register Reset Value 00H 7 6 5 4 3 2 1 0 P7 P6...

Page 186: ...ster Full Name P4_DATA Port 4 Data Register P4_DIR Port 4 Direction Register P4_OD Port 4 Open Drain Control Register P4_PUDSEL Port 4 Pull Up Pull Down Select Register P4_PUDEN Port 4 Pull Up Pull Do...

Page 187: ...ALT3 TXDC0_3 MultiCAN P4 21 Input GPI P4_DATA P2 ALT1 T21_0 Timer 21 ALT2 EXINT6_1 External Interrupt 6 ALT3 Output GPO P4_DATA P2 ALT1 ALT2 ALT3 P4 3 Input GPI P4_DATA P3 ALT1 ALT2 ALT3 Output GPO P...

Page 188: ...T1 CC61_4 CCU6 ALT2 ALT3 P4 51 Input GPI P4_DATA P5 ALT1 CCPOS1_3 CCU6 ALT2 T1_0 Timer 1 ALT3 Output GPO P4_DATA P5 ALT1 COUT61_2 CCU6 ALT2 ALT3 P4 61 Input GPI P4_DATA P6 ALT1 CCPOS2_3 CCU6 ALT2 T2_0...

Page 189: ...0 P4 71 Input GPI P4_DATA P7 ALT1 CTRAP_3 CCU6 ALT2 ALT3 Output GPO P4_DATA P7 ALT1 COUT62_2 CCU6 ALT2 ALT3 1 Pins P4 2 P4 4 to P4 7 are only available only in XC888 Table 6 12 Port 4 Input Output Fu...

Page 190: ...Value 00H 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 rw rw rw rw rw rw rw rw Field Bits Type Description Pn n 0 7 n rw Port 4 Pin n Data Value 0 Port 4 pin n data value 0 default 1 Port 4 pin n data valu...

Page 191: ...7 n rw Port 4 Pin n Open Drain Mode 0 Normal mode output is actively driven for 0 and 1 states default 1 Open drain mode output is actively driven only for 0 state P4_PUDSEL Port 4 Pull Up Pull Down...

Page 192: ...rw rw rw Field Bits Type Description Pn n 0 7 n rw Pull Up Pull Down Enable at Port 4 Bit n 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled P4_ALTSELn n 0 1 Port 4...

Page 193: ...ter Short Name Register Full Name P5_DATA Port 5 Data Register P5_DIR Port 5 Direction Register P5_OD Port 5 Open Drain Control Register P5_PUDSEL Port 5 Pull Up Pull Down Select Register P5_PUDEN Por...

Page 194: ...rrupt 2 ALT3 Output GPO P5_DATA P1 ALT1 ALT2 ALT3 P5 2 Input GPI P5_DATA P2 ALT1 RXD_2 UART ALT2 ALT3 Output GPO P5_DATA P2 ALT1 ALT2 ALT3 P5 3 Input GPI P5_DATA P3 ALT1 ALT2 ALT3 Output GPO P5_DATA P...

Page 195: ...ALT1 ALT2 RXDO_2 UART ALT3 P5 5 Input GPI P5_DATA P5 ALT1 ALT2 ALT3 Output GPO P5_DATA P5 ALT1 TDO_2 JTAG ALT2 TXD1_2 UART1 ALT3 P5 6 Input GPI P5_DATA P6 ALT1 TCK_2 JTAG ALT2 ALT3 Output GPO P5_DATA...

Page 196: ...V1 3 2010 02 Parallel Ports V 1 0 P5 7 Input GPI P5_DATA P7 ALT1 TDI_2 JTAG ALT2 RXD1_2 UART1 ALT3 Output GPO P5_DATA P7 ALT1 ALT2 ALT3 Table 6 14 Port 5 Input Output Functions cont d Port Pin Input O...

Page 197: ...rw rw rw rw rw rw Field Bits Type Description Pn n 0 7 n rw Port 5 Pin n Data Value 0 Port 5 pin n data value 0 default 1 Port 5 pin n data value 1 P5_DIR Port 5 Direction Register Reset Value 00H 7 6...

Page 198: ...7 n rw Port 5 Pin n Open Drain Mode 0 Normal mode output is actively driven for 0 and 1 states default 1 Open drain mode output is actively driven only for 0 state P5_PUDSEL Port 5 Pull Up Pull Down...

Page 199: ...Down Enable at Port 5 Bit n 0 Pull up or Pull down device is disabled 1 Pull up or Pull down device is enabled P5_ALTSELn n 0 1 Port 5 Alternate Select Register Reset Value 00H 7 6 5 4 3 2 1 0 P7 P6...

Page 200: ...Phase Locked Loop PLL and oscillator units In phase synchronized clock signals are derived from the master clock and distributed throughout the system A programmable clock divider is available for sca...

Page 201: ...ICON NMIVDD If VDDC is below 2 1 V the brownout reset is activated putting the microcontroller into a reset state For VDDP there is only one prewarning threshold of 4 0 V if the external power supply...

Page 202: ...wake up reset While the contents of the static RAM are undefined after a power on reset they are well defined after a wake up reset from power down mode A brownout reset is triggered if the VDDC suppl...

Page 203: ...ill run at its base frequency Once the EVR is stable provided the oscillator is running the PLL is connected and the continuous lock detection ensures that PLL starts functioning Following this as soo...

Page 204: ...the same as the power on reset sequence as shown in Figure 7 4 A hardware reset through RESET pin will terminate the idle mode or the power down mode The status of pins MBC TMS and P0 0 is latched by...

Page 205: ...ated by the PMCON0 WKRS bit Figure 7 5 shows the power down wake up reset sequence The EVR takes approximately 150 s to become stable which is a shorter time period compared to the power on reset Figu...

Page 206: ...that the particular function is reset to its default state Table 7 1 Effect of Reset on Device Functions Module Function Wake Up Reset Watchdog Reset Hardware Reset Power On Reset Brownout Reset CPU...

Page 207: ...lect the different boot options Table 7 2 shows the available boot options in the XC886 888 Note The boot options are valid only with the default set of UART and JTAG pins Table 7 2 XC886 888 Boot Sel...

Page 208: ...Table 7 3 7 6 5 4 3 2 1 0 0 WDTRST WKRS WKSEL SD PD WS r rwh rwh rw rw rwh rw Field Bits Type Description WS 1 0 rw Wake Up Source Select 00 No wake up is selected 01 Wake up source RXD falling edge...

Page 209: ...r Reset and Clock V 1 0 WDTRST 6 rwh Watchdog Timer Reset Indication Bit 0 No watchdog timer reset occurred 1 Watchdog timer reset has occurred This bit can only be set by hardware and reset by softwa...

Page 210: ...Locked Loop PLL In the XC886 888 the oscillator can be from either of these two sources the on chip oscillator 9 6 MHz or the external oscillator 4 MHz to 12 MHz The term oscillator is used to refer...

Page 211: ...iately via the NMI routine upon PLL Loss of Lock to force PLL to run in VCO base frequency Emergency routines can be executed with the XC886 888 clocked with this base frequency The XC886 888 remains...

Page 212: ...lator Run Detection by setting bit OSC_CON ORDRES 7 Wait for 2048 cycles based on VCO frequency If bit OSC_CON OSCR is set then continue with the sequence below Else repeat the sequence from step 6 1...

Page 213: ...de The system clock is derived from the oscillator clock divided by the P factor multiplied by the N factor and divided by the K factor 7 3 Table 7 4 shows the settings of bits OSCDISC and VCOBYP for...

Page 214: ...tes all clock signals required within the microcontroller from the basic clock It consists of Basic clock slow down circuitry Centralized enable disable circuit for clock control Figure 7 7 shows the...

Page 215: ...can further be divided by 2 using toggle latch bit TLEN is set to 1 so that the resulting output frequency has 50 duty cycle In idle mode only the CPU clock CCLK is disabled In power down mode CCLK S...

Page 216: ...ate of the oscillator run detection 0 The oscillator is not running 1 The oscillator is running ORDRES 1 rwh Oscillator Run Detection Reset 0 No operation 1 The oscillator run detection logic is reset...

Page 217: ...RESLD 1 rwh Restart Lock Detection Setting this bit will reset the PLL lock status flag and restart the lock detection This bit will automatically be reset to 0 and thus always be read back as 0 0 No...

Page 218: ...01B will be observed NDIV 7 4 rw PLL N Divider 0000 N 10 0001 N 12 0010 N 13 0011 N 14 0100 N 15 0101 N 16 0110 N 17 0111 N 18 1000 N 19 1001 N 20 1010 N 24 1011 N 30 1100 N 32 1101 N 36 1110 N 40 111...

Page 219: ...YS 768 Note The clock division factors listed above is inclusive of the fixed divider factor of 2 See Figure 7 7 FCCFG 4 rw Fast Clock Configuration 0 FCLK runs at the same frequency as PCLK 1 FCLK ru...

Page 220: ...YS 18 1011 fSYS 20 1100 fSYS 24 1101 fSYS 32 1110 fSYS 36 1111 fSYS 40 COUTS 4 rw Clock Out Source Select 0 Oscillator output frequency is selected 1 Clock output frequency is chosen by the bit field...

Page 221: ...86 888CLM Power Supply Reset and Clock Management User s Manual 7 22 V1 3 2010 02 Power Reset and Clock V 1 0 Note Registers OSC_CON PLL_CON CMCON and COCON are not reset during the watchdog timer res...

Page 222: ...er down of the entire system with fast restart capability After a reset the active mode normal operating mode is selected by default see Figure 8 1 and the system runs in the main system clock frequen...

Page 223: ...nabled interrupt The CPU operation is resumed and the interrupt will be serviced Upon RETI instruction the core will return to execute the next instruction after the instruction that sets the IDLE bit...

Page 224: ...nce it cannot be awakened by an interrupt or by the WDT It is awakened only when it receives an external wake up signal or reset signal Entering Power down Mode Software requests power down mode by se...

Page 225: ...ake up from power down without reset undergoes the following procedure 1 In power down mode EXINT0 pin RXD pin must be held at high level 2 Power down mode is exited when EXINT0 pin RXD pin goes low f...

Page 226: ...CON1 register Furthermore the analog part of the ADC module may be disabled by resetting the GLOBCTR ANON bit This feature causes the generation of fADCI to be stopped and allows a reduction in power...

Page 227: ...t is a protected bit When the Protection Scheme is activated this bit cannot be written directly WKSEL 4 rw Wake up Reset Select Bit 0 Wake up without reset 1 Wake up with reset WKRS 5 rwh Wake up Ind...

Page 228: ...r Input RXD_2 is selected 11 Reserved EXINT0IS 1 rw External Interrupt 0 Input Select 0 External Interrupt Input EXINT0_0 is selected 1 External Interrupt Input EXINT0_1 is selected 0 7 r Reserved Ret...

Page 229: ...in normal operation default 1 CAN is disabled CDC_DIS 6 rw CORDIC Disable Request Active high 0 CORDIC is in normal operation default 1 CORDIC is disabled 0 7 r Reserved Returns 0 if read should be w...

Page 230: ...re not possible To achieve minimal power consumption the internal analog circuitry is in its power down state and the generation of fADCI is stopped 1 The analog part of the ADC module is switched on...

Page 231: ...1 3 2010 02 Power Saving Modes V 1 0 OSCPD 4 rw On chip OSC Power down Control 0 The on chip oscillator is not powered down 1 The on chip oscillator is powered down 0 7 5 r Reserved Returns 0 if read...

Page 232: ...system reset Hence routine service of the WDT confirms that the system is functioning properly This ensures that an accidental malfunction of the XC886 888 will be aborted in a user specified time pe...

Page 233: ...ws a system malfunction is assumed and normal mode is terminated A WDT NMI request FNMIWDT is then asserted and prewarning is entered The prewarning lasts for 30H count During the prewarning period re...

Page 234: ...register WDTCON to be either fPCLK 2 or fPCLK 128 The reload value WDTREL for the high byte of WDT can be programmed in register WDTREL The period PWDT between servicing the WDT and the next overflow...

Page 235: ...debug mode by clearing the bit WDTSUSP in SFR MODSUSP to 0 Table 9 1 Watchdog Time Ranges Reload value in WDTREL Prescaler for fWDT 2 WDTIN 0 128 WDTIN 1 24 MHz 16 MHz 12 MHz 24 MHz 16 MHz 12 MHz FFH...

Page 236: ...trolled by its bitaddressable WDT Control Register WDTCON This register also selects the input clock prescaling factor The register WDTREL specifies the reload value for the high byte of the timer Tab...

Page 237: ...able WDTEN is a protected bit If the Protection Scheme see Chapter 3 5 4 1 is activated then this bit cannot be written directly 0 WDT is disabled 1 WDT is enabled WDTPR 4 rh Watchdog Prewarning Mode...

Page 238: ...atchdog Timer Low Byte Reset Value 00H 7 6 5 4 3 2 1 0 WDT 7 0 rh Field Bits Type Description WDT 7 0 7 0 rh Watchdog Timer Current Value WDTH Watchdog Timer High Byte Reset Value 00H 7 6 5 4 3 2 1 0...

Page 239: ...H the WDT cannot do a Refresh else it will cause a WDTRST to be asserted WDTWINB is matched to WDTH PMCON0 Power Mode Control Register 0 Reset Value See 00H 1 1 The reset value for watchdog timer rese...

Page 240: ...any other registers for peripheral control The MDU operates concurrently with and independent of the CPU Features Fast signed unsigned 16 bit multiplication Fast signed unsigned 32 bit divide by 16 bi...

Page 241: ...CON OPCODE Phase two Execute calculation This phase commences only when the start bit MDUCON START is set which in turn sets the busy flag The start bit is automatically cleared in the next cycle Duri...

Page 242: ...gisters MD0 to MD3 are removed by shift left operations The whole operation is completed when the MSB most significant bit contains a 1 After normalizing bit field MR4 SCTR contains the number of shif...

Page 243: ...e to division by zero lead to the loading of a saturated value into the MRx registers Note The accuracy of any result obtained when the error flag is set is not guaranteed by MDU and hence the result...

Page 244: ...ow Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00H 7 6 5 4 3 2 1 0 0 CDC_DIS CAN_DIS MDU_DIS T2_DIS CCU_DIS SSC_DIS ADC_DIS r rw...

Page 245: ...a read operation an additional bit MDUCON RSEL is needed to select which set of registers MDx or MRx the read operation must be directed to By default the MRx registers are read Table 10 2 MDU Registe...

Page 246: ...multiplicator must be written to register MD4 and the high byte to MD5 Abbreviations D end Dividend 1st operand of division Table 10 3 MDx Registers Register Roles of registers in operations 16 bit Mu...

Page 247: ...ans that this byte is the most significant of the 16 bit or 32 bit operand The MDx registers are built with shadow registers which are latched with data from the actual registers at the start of a cal...

Page 248: ...input and output control registers for shift and normalize operations MDx x 0 5 MDU Operand Register Reset Value 00H 7 6 5 4 3 2 1 0 DATA rw Field Bits Type Description DATA 7 0 rw Operand Value See...

Page 249: ...ion SLR 5 rw Shift Direction 0 Selects shift left operation 1 Selects shift right operation 0 7 6 rw Reserved Should be written with 0 Returns undefined data if read MR4 Shift Output Control Register...

Page 250: ...bit 16 bit Division 0010 Unsigned 32 bit 16 bit Division 0011 32 bit Logical Shift L R 0100 Signed 16 bit Multiplication 0101 Signed 16 bit 16 bit Division 0110 Signed 32 bit 16 bit Division 0111 32 b...

Page 251: ...DUCON is not allowed when the busy flag MDUSTAT BSY is set during the calculation phase Note Writing reserved opcode values to MDUCON results in an error condition when MDUCON START bit is set to 1 IE...

Page 252: ...set by hardware and reset by software 0 No interrupt is triggered at the end of a successful operation 1 An interrupt is triggered at the end of a successful operation IERR 1 rwh Interrupt on Error Th...

Page 253: ...gorithm is the low hardware costs involved compared to other complex algorithms The generalized CORDIC algorithm has the following CORDIC equations The factor m controls the vector rotation and select...

Page 254: ...tion 16 iterations per calculation Approximately 41 clock cycles or less from set of start ST bit to set of end of calculation flag excluding time taken for write and read access of data bytes Twos co...

Page 255: ...ng calculation Values are transferred to the kernel data registers only on valid setting of bit ST or if ST_MODE 0 after write access to X low byte CD_CORDXL provided KEEP bit of corresponding data is...

Page 256: ...d the interpretation for Z result data differs which is also dependent on the CORDIC function used For linear function there is no additional processing of the CORDIC calculated Z data as such it is t...

Page 257: ...ign yi yi 0 Circular m 1 ei atan 2 i Xfinal K X cos Z Y sin Z MPS Yfinal K Y cos Z X sin Z MPS Zfinal 0 where K 1 64676 Xfinal K sqrt X2 Y2 MPS Yfinal 0 Zfinal Z atan Y X where K 1 64676 For solving c...

Page 258: ...and larger than the initial data is X result data only in circular vectoring mode therefore the user may want to use the MSB bit as data bit instead of sign bit By setting X_USIGN 1 X result data wil...

Page 259: ...zero In other words the CORDIC Coprocessor is not able to return accurate result for cosh Z sinh Z in a single calculation 11 2 4 1 Domains of Convergence For convergence of result data there are limi...

Page 260: ...ctions any value of Z outside of the range 215 1 215 cannot be represented and will result in Z data overflow error Note that kernel data Z has values in the range 219 1 219 scaled to the range 219 21...

Page 261: ...al number the magnitude of deviation has to be interpreted For example Z for linear vectoring mode of the data form S4 11 ND 1 01B means the difference from expected real data has magnitude of no more...

Page 262: ...Useful Domain Full range of X Y and Z 0 50 7715 1 48 8579 2 0 3681 3 0 0023 4 0 0002 ND for X 4 0 51 2011 1 48 4944 2 0 3024 3 0 0020 4 0 0001 ND for Y 4 Linear Vectoring Input conditions Useful Domai...

Page 263: ...of 16 iterations per calculation the total time from the start of calculation to the instant the EOC flag is set is approximately 41 clock cycles or less It should be noted that the ERROR flag is vali...

Page 264: ...ted LUT as mentioned above is actually a shift register that generates data by shifting This shift register is reloaded whenever the Finite State Machine FSM switches to the setup mode on starting a n...

Page 265: ...lated LUT for linear function is actually a shift register The emulated LUT has 1 integer bit MSB followed by 15 bit fractional part of the form 1Q16 In linear function where Z is a real number the in...

Page 266: ...setting bit CDC_DIS in register PMCON1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00H 7 6 5 4 3 2 1 0 0 CDC_D...

Page 267: ...bed in this section shall be referenced fully with the module name prefix CD_ Table 11 6 Register Summary for CORDIC Coprocessor Name Address HEX Reset Value HEX Description CD_CORDXL 9A 00 CORDIC X D...

Page 268: ...h Field Bits Type Description ST 0 rwh Start Calculation If ST_MODE 1 set ST to start a CORDIC calculation Is effective only while BSY is not set This bit may be set with the other bits of this regist...

Page 269: ...ular vectoring mode In all other modes X is always processed as twos complement data Note X_USIGN 1 is meaningful in circular vectoring mode because the result data is always positive and always large...

Page 270: ...ne clock cycle after bit ST was set It is deasserted at the end of a calculation ERROR 1 rh Error Indication In case of overflow error in the calculated result for X Y or Z this bit is set at the end...

Page 271: ...words the respective kernel data register will not be overwritten by the contents of the shadow data register at the beginning of new calculation This bit should always be cleared for the very first c...

Page 272: ...ation For read DMAP 0 Result data from kernel data byte DMAP 1 Initial data from the shadow data byte CD_CORDxH x X Y or Z CORDIC x Data High Byte Reset Value 00H 7 6 5 4 3 2 1 0 DATAH rw Field Bits T...

Page 273: ...buffered Multiprocessor communication Interrupt generation on the completion of a data transmission or reception LIN Features Master and slave mode operation SSC Features Master and slave mode operati...

Page 274: ...either the underflow rate on the dedicated baud rate generator or by the overflow rate on Timer 1 The different modes are selected by setting bits SM0 and SM1 to their corresponding values as shown in...

Page 275: ...as in mode 0 At phase 1 of the machine cycle after the next rollover in the divide by 16 counter the start bit is copied to TXD and data is activated one bit time later One bit time after the data is...

Page 276: ...2 Serial Interfaces V 1 0 Figure 12 1 Serial Interface Mode 1 Timing Diagram D0 D1 D2 D3 D4 D5 D6 D7 Start Bit Stop Bit TX Clock Data Shift TXD TI D0 D1 D2 D3 D4 D5 D6 D7 Start Bit Stop Bit RX Clock R...

Page 277: ...s it is shifted into the register followed by 8 data bits If the transition is not followed by a valid start bit the controller goes back to looking for a high to low transition on RXD When the start...

Page 278: ...l Interfaces V 1 0 Figure 12 2 Serial Interface Modes 2 and 3 Timing Diagram D0 D1 D2 D3 D4 D5 D6 TB8 Start Bit Stop Bit TX Clock Data Shift TXD TI D0 D1 D2 D3 D4 D5 D6 RB8 Start Bit Stop Bit RX Clock...

Page 279: ...raph When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte that identifies the target slave An address byte differs from a data byte i...

Page 280: ...ce Writing to SBUF loads the transmit register and initiates transmission This register is used for both transmit and receive data Transmit data is written to this location and receive data is read fr...

Page 281: ...he 9th data bit sent REN 4 rw Enable Receiver of Serial Port 0 Serial reception is disabled 1 Serial reception is enabled SM2 5 rw Enable Serial Port Multiprocessor Communication in Modes 2 and 3 In m...

Page 282: ...ed However for the case of UART module while the baud rate in mode 0 can only be fPCLK 2 the baud rate in mode 2 can be selected as either fPCLK 64 or fPCLK 32 depending on bit SMOD Bit SMOD in the PC...

Page 283: ...fDIV if the fractional divider is disabled FDEN 0 For baud rate generation the fractional divider must be configured to fractional divider mode FDCON FDM 0 This allows the baud rate control run bit BC...

Page 284: ...put clock fPCLK Prescaling factor 2BRPRE defined by bit field BRPRE in register BCON Fractional divider STEP 256 defined by register FDSTEP to be considered only if fractional divider is enabled and o...

Page 285: ...Table 12 2 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors The fractional divider is disabled and a module clock of 24 MHz is used The fract...

Page 286: ...a factor of n 256 where n is defined by bit field STEP in register FDSTEP and can take any value from 0 to 255 In fractional divider mode the output clock pulse fMOD is dependent on the result of the...

Page 287: ...e fractional divider is enabled FDEN 1 it functions as an 8 bit auto reload timer with no relation to baud rate generation and counts up from the reload value with each input clock pulse Bit field RES...

Page 288: ...ts for the baud rate generator and the prescaling factor BCON Baud Rate Control Register Reset Value 00H 7 6 5 4 3 2 1 0 BGSEL 0 BRDIS BRPRE R rw r rw rw rw Field Bits Type Description R 0 rw Baud rat...

Page 289: ...d by the following formula fPCLK 2184 2 BGSEL baud rate range fPCLK 72 2 BGSEL where BGSEL 00B 01B 10B 11B See Table 12 4 for bit field BGSEL definition for different input frequencies 0 5 r Reserved...

Page 290: ...3 kHz selected BGSEL value is 00B If the baud rate is 20kHz the possible values of BGSEL that can be selected are 00B 01B 10B and 11B However it is advisable to select 00B for better detection accurac...

Page 291: ...w Fractional Divider Mode Select 0 Fractional Divider Mode is selected 1 Normal Divider Mode is selected NDOV 2 rwh Overflow Flag in Normal Divider Mode This bit is set by hardware and can only be cle...

Page 292: ...d SYN Byte Error Interrupts Enable 0 End of SYN Byte and SYN Byte Error Interrupts are not enabled 1 End of SYN Byte and SYN Byte Error Interrupts are enabled BGS 7 rw Baud rate Generator Select 0 Bau...

Page 293: ...ider FDRES Fractional Divider Result Register Reset Value 00H 7 6 5 4 3 2 1 0 RESULT rh Field Bits Type Description RESULT 7 0 rh RESULT Value In normal divider mode RESULT acts as reload counter addi...

Page 294: ...and the value of SMOD as follows 12 6 Alternatively for a given baud rate the value of Timer 1 high byte can be derived 12 7 Note Timer 1 can neither indicate an overflow nor generate an interrupt if...

Page 295: ...EXINT1IS EXINT0IS URRIS r rw rw rw rw rw rw rw Field Bits Type Description URRISH URRIS 6 0 rw UART Receive Input Select 6 0 00 UART Receiver Input RXD_0 is selected 01 UART Receiver Input RXD_1 is se...

Page 296: ...to Chapter 8 1 4 for details on peripheral clock management Note The Low Power Mode option is not available in UART module 0 6 5 r Reserved Returns 0 if read should be written with 0 PMCON2 Power Mode...

Page 297: ...prefix Besides the SCON and SBUF registers which can be accessed from both the standard non mapped and mapped SFR area the rest of the UART module s SFRs are located in SCU page 0 of the standard area...

Page 298: ...nication is based on the SCI UART data format a single master multiple slave concept a clock synchronization for nodes without stabilized time base An attractive feature of LIN is self synchronization...

Page 299: ...st one nominal bit time long A slave node will use a break detection threshold of 11 nominal bit times Figure 12 8 The Break Field Synch Byte is a specific pattern for determination of time base The b...

Page 300: ...ant value of 13 bits or more to ensure proper synchronization of slave nodes In the LIN communication a slave task is required to be synchronized at the beginning of the protected identifier field of...

Page 301: ...nts are enabled T2CON EXEN2 is set to 1 EXF2 flag is set when a negative transition occurs at pin T2EX fT2 can be configured by bit field T2MOD T2PRE The baud rate detection for LIN is shown in Figure...

Page 302: ...tation Then the LIN routine calculates the actual baud rate sets the PRE and BG values if the UART module uses the baud rate generator for baud rate generation After the third falling edge the softwar...

Page 303: ...ines TXD and RXD which are normally connected to the pins MTSR Master Transmit Slave Receive and MRST Master Receive Slave Transmit The clock signal is output via line MS_CLK Master Serial Shift Clock...

Page 304: ...er of bits 2 8 have been transferred the contents of the shift register are moved to the Receiver Buffer register RB and the Receive Interrupt Request line RIR will be activated If no further transfer...

Page 305: ...e The Clock Control allows the transmit and receive behavior of the SSC to be adapted to a variety of serial interfaces A specific shift clock edge rising or falling is used to shift out transmit data...

Page 306: ...eceive line in the configuration shown in Figure 12 13 During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different...

Page 307: ...latches and shifts in the data detected at its input line RXD This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shi...

Page 308: ...ne data exchange line serial data may be moved between arbitrary stations As in full duplex mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enabl...

Page 309: ...n will start without any additional delay On the data line there is no gap between the two successive frames For example two byte transfers would look the same as one word transfer This feature can be...

Page 310: ...operating mode The SSC will automatically use the correct kernel output or kernel input line of the ports when switching modes Since the SSC I O lines are connected with the bidirectional lines of the...

Page 311: ...ired reload value can be written to BR Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload value...

Page 312: ...24 MHz Reload Value Baud Rate fMS_CLK SS_CLK Deviation 0000H 12 MBaud only in Master mode 0 0 0001H 6 MBaud 0 0 0008H 1 3 MBaud 0 0 000BH 1 MBaud 0 0 000FH 750 kBaud 0 0 0011H 666 7 kBaud 0 0 0013H 60...

Page 313: ...ther must be cleared by software after servicing This allows servicing of error conditions to be done via interrupt if their enable bits are set or via polling by software if their enable bits are not...

Page 314: ...that the SSC module supports back to back transfers for multiple transfers In order to handle this the baud rate detector expects immediately after a finished transfer the next clock cycle for a new...

Page 315: ...receive buffer Receive Error EIR This interrupt occurs if a new data frame is completely received and the last data in the receive buffer was not read Phase Error EIR This interrupt is generated if t...

Page 316: ...peripheral clock management 12 3 4 Register Map The addresses of the kernel SFRs are listed in Table 12 8 PMCON1 Power Mode Control Register 1 Reset Value 00H 7 6 5 4 3 2 1 0 0 CDC_DIS CAN_DIS MDU_DI...

Page 317: ...f the SSC module PISEL Port Input Select Register Reset Value 00H 7 6 5 4 3 2 1 0 0 CIS SIS MIS r rw rw rw Field Bits Type Description MIS 0 rw Master Mode Receiver Input Select 0 Receiver input P1 4...

Page 318: ...rw rw rw rw rw Field Bits Type Description BM 3 0 rw Data Width Selection 0000 Reserved Do not use this combination 0001 0111 Transfer Data Width is 2 8 bits BM 1 Note BM 3 is fixed to 0 HB 4 rw Head...

Page 319: ...rrupt is enabled PEN 2 rw Phase Error Enable 0 Phase error interrupt is disabled 1 Phase error interrupt is enabled BEN 3 rw Baud Rate Error Enable 0 Baud rate error interrupt is disabled 1 Baud rate...

Page 320: ...0 7 4 r Reserved Returns 0 if read should be written with 0 CONH Control Register High Reset Value 00H 7 6 5 4 3 2 1 0 EN MS 0 BSY BE PE RE TE rw rw r rh rwh rwh rwh rwh Field Bits Type Description T...

Page 321: ...N ensure that reserved locations receive zeros BE 3 rwh Baud rate Error Flag 0 No error 1 More than factor 2 or 0 5 between slave s actual and expected baud rate BSY 4 rh Busy Flag Set while a transfe...

Page 322: ...d Bits Type Description BR_VALUE 7 0 rw Baud Rate Timer Reload Register Value 7 0 Reading BR returns the 16 bit contents of the baud rate timer Writing to BR loads the baud rate timer reload register...

Page 323: ...uffer Register Low Reset Value 00H 7 6 5 4 3 2 1 0 TB_VALUE rw Field Bits Type Description TB_VALUE 7 0 rw Transmit Data Register Value TB_VALUE is the data value to be transmitted Unselected bits of...

Page 324: ...XC886 888CLM Serial Interfaces User s Manual 12 52 V1 3 2010 02 Serial Interfaces V 1 0...

Page 325: ...s counting events and generating signals at regular intervals In particular Timer 1 can be used as the baud rate generator for the on chip serial port Timer 0 and Timer 1 Features Four operational mod...

Page 326: ...low byte and THx high byte which defaults to 00H on reset Setting or clearing TCON TRx does not affect the timer registers Timer Overflow When a timer overflow occurs the timer overflow flag TCON TFx...

Page 327: ...0 and Timer 1 Modes Mode Operation 0 13 bit timer counter The timer is essentially an 8 bit counter with a divide by 32 prescaler This mode is included solely for compatibility with Intel 8048 devices...

Page 328: ...input is enabled for the timer when TRx 1 and either GATEx 0 or EXINTx 1 setting GATEx 1 allows the timer to be controlled by external input EXINTx to facilitate pulse width measurements TRx is a con...

Page 329: ...eration is similar to that of mode 0 except that the timer register runs with all 16 bits Mode 1 operation for Timer 0 is shown in Figure 13 2 Figure 13 2 Timer 0 Mode 1 16 Bit Timer Counter TL0 8Bits...

Page 330: ...reload as shown in Figure 13 3 for Timer 0 An overflow from TLx not only sets TFx but also reloads TLx with the contents of THx that has been preset by software The reload leaves THx unchanged Figure...

Page 331: ...0 while TH0 is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus TH0 now sets TF1 upon overflow and generates an interrupt if ET1 is set Mode...

Page 332: ...d T1_1 for Timer 1 This selection is performed by the SFR bits MODPISEL2 T0IS and MODPISEL2 T1IS MODPISEL2 Peripheral Input Select Register 2 Reset Value 00H 7 6 5 4 3 2 1 0 0 T2IS T2IS T1IS T0IS r r...

Page 333: ...Map Seven SFRs control the operations of Timer 0 and Timer 1 They can be accessed from both the standard non mapped and mapped SFR area Table 13 2 lists the addresses of these SFRs Table 13 2 Register...

Page 334: ...oth timers are selected using register TMOD Register IEN0 contains bits that enable interrupt operations in Timer 0 and Timer 1 TLx x 0 1 Timer x Low Byte Reset Value 00H 7 6 5 4 3 2 1 0 VAL rwh Field...

Page 335: ...T1 IE0 IT0 r r rwh rw rwh rw rwh rw rwh rw Field Bits Type Description TR0 4 rw Timer 0 Run Control 0 Timer is halted 1 Timer runs TF0 5 rwh Timer 0 Overflow Flag Set by hardware when Timer 0 overflow...

Page 336: ...ard Timer 1 control bits TH1 and TL1 of Timer 1 are held Timer 1 is stopped T1M 5 4 rw Mode select bits 00 13 bit timer M8048 compatible mode 01 16 bit timer 10 8 bit auto reload timer 11 Timer 0 is s...

Page 337: ...N TR1 is set IEN0 Interrupt Enable Register Reset Value 00H 7 6 5 4 3 2 1 0 EA 0 ET2 ES ET1 EX1 ET0 EX0 r rw r rw rw rw rw rw rw Field Bits Type Description ET0 1 rw Timer 0 Overflow Interrupt Enable...

Page 338: ...eloads its register contents with a 16 bit start value for a fresh counting sequence The overflow condition is indicated by setting bit TF2 in the T2CON register At the same time an interrupt request...

Page 339: ...T2REGS If bit EXEN2 is set bit EXF2 is also set at the same point when Timer 2 is started with the same falling edge rising edge at pin T2EX which is defined by bit EDGESEL The reload will happen with...

Page 340: ...2EX sets the Timer 2 to down counting mode The timer counts down and underflows when the THL2 value reaches the value stored at register RC2 The underflow condition sets the TF2 flag and causes FFFFH...

Page 341: ...Manual 13 17 V1 3 2010 02 Timers V 1 0 Figure 13 6 Auto Reload Mode DCEN 1 TF2 EXF2 THL2 OR TR2 Overflow Timer 2 Interrupt 16 bit Comparator FFFFH Down count reload Underflow RC2 T2EX fPCLK PREN T2PR...

Page 342: ...ed input shows a low high level in one PCLK cycle and a high low in the next PCLK cycle a transition is recognized If the capture signal is detected while the counter is being incremented the counter...

Page 343: ...of input pin T2 The counter samples pin T2 over 2 PCLK cycles If a 1 was detected during the first clock and a 0 was detected in the following clock then the counter increments by one Therefore the i...

Page 344: ...ternal interrupt function with bit EXF2 serving as the external interrupt flag 13 2 6 Port Control When functioning as an event counter Timer 2 and Timer 21 count 1 to 0 transitions at their external...

Page 345: ...l Register 1 Reset Value 00H 7 6 5 4 3 2 1 0 0 CDC_DIS CAN_DIS MDU_DIS T2_DIS CCU_DIS SSC_DIS ADC_DIS r rw rw rw rw rw rw rw Field Bits Type Description T2_DIS 3 rw Timer 2 Disable Request Active high...

Page 346: ...ts T2SUSP and T21SUSP in SFR MODSUSP MODSUSP Module Suspend Control Register Reset Value 01H 7 6 5 4 3 2 1 0 0 T21SUSP T2SUSP T13SUSP T12SUSP WDTSUSP r rw rw rw rw rw Field Bits Type Description T2SUS...

Page 347: ...with the module name prefix T2_ e g T2_T2CON while those of Timer 21 are referenced with T21_ e g T21_T2CON The Timer 2 SFRs are located in the standard non mapped SFR area The corresponding set of SF...

Page 348: ...1 Down 0 T2PRE 3 1 rw Timer 2 Prescaler Bit Selects the input clock for Timer 2 which is derived from the peripheral clock 000 fT2 fPCLK 001 fT2 fPCLK 2 010 fT2 fPCLK 4 011 fT2 fPCLK 8 100 fT2 fPCLK 1...

Page 349: ...ld Bits Type Description CP RL2 0 rw Capture Reload Select 0 Reload upon overflow or upon negative positive transition at pin T2EX when EXEN2 1 1 Capture Timer 2 data register contents on the negative...

Page 350: ...itive transition occurs at pin T2EX if bit EXEN2 1 This bit must be cleared by software Note When bit DCEN 1 in auto reload mode no interrupt request to the core is generated TF2 7 rwh Timer 2 Overflo...

Page 351: ...these contents are loaded into the timer register upon an overflow condition If CP RL2 1 this register is loaded with the current timer count upon a negative positive transition at pin T2EX when EXEN2...

Page 352: ...imer 2 Register Low Reset Value 00H 7 6 5 4 3 2 1 0 THL2 rwh Field Bits Type Description THL2 7 0 rwh Timer 2 Value 7 0 These bits indicate the current timer value T2H Timer 2 Register High Reset Valu...

Page 353: ...eneration of a three phase PWM six outputs individual signals for highside and lowside switches 16 bit resolution maximum count frequency peripheral clock frequency Dead time control for each channel...

Page 354: ...t output control CC62 COUT62 CC61 COUT61 CC60 COUT60 COUT63 CTRAP channel 3 T13 CCPOS0 1 1 1 2 2 2 1 start compare capture 3 multi channel control address decoder clock control interrupt control trap...

Page 355: ...he internal Shadow Period Register T12PS to prepare another period value The transfer from the shadow registers to the actual registers is enabled by setting the shadow transfer enable bit STE12 If th...

Page 356: ...ction defined by bit T12SSC If bit T12SSC 1 the bit T12R is reset by hardware when T12 reaches its period value in edge aligned mode T12 reaches the value 1 while counting down in center aligned mode...

Page 357: ...active AND active active active AND passive passive passive AND passive passive The compare states change with the detected compare matches and are indicated by the CC6xST bits The compare states of T...

Page 358: ...an be set if it is 0 by the following events a software set MCC6xS a compare set event T12 counter value above the compare value if the T12 runs and if the T12 set event is enabled upon a capture set...

Page 359: ...COUT6x COUT6xPS 1 PSL 0 active active active passive passive passive CCU6_T12_comp_states CC60PS 0 COUT60PS 1 PSL0 0 PSL1 0 CC6xPS 0 COUT6xPS 1 PSL0 1 PSL1 0 CC6xPS 0 COUT6xPS 1 PSL0 1 PSL1 1 CC6xPS 0...

Page 360: ...ad time and the complete duty cycle range of 0 to 100 in edge aligned and center aligned modes 14 1 1 5 Duty Cycle of 0 and 100 These counting and switching rules ensure a PWM functionality in the ful...

Page 361: ...three channels works independently with its own dead time counter trigger and enable signals The value of bit field DTM is valid for all three channels 14 1 1 7 Capture Mode In capture mode the bits C...

Page 362: ...shot mode the timer T12 stops automatically at the end of its counting period Figure 14 7 shows the functionality at the end of the timer period in edge aligned and center aligned modes If the end of...

Page 363: ...cts if a value exceeds a limit and switches its output according to the compare result Depending on the operating conditions the switching frequency and the duty cycle may change constantly Figure 14...

Page 364: ...ritten by software The bits CC63PS T13IM and PSL63 have shadow bits The contents of these shadow bits are transferred to the actually used bits during the T13 shadow transfer Write actions target the...

Page 365: ...nter actions depend on the defined counting rules The bit CC63ST indicates the occurrence of a compare event of the corresponding channel It can be set if it is 0 by the following events a software se...

Page 366: ...3 This event sets bit T13R by hardware and T13 starts counting Combined with the single shot mode this can be used to generate a programmable delay after a T12 event Figure 14 10 Synchronization of T1...

Page 367: ...utput line during the trap state if enabled Figure 14 11 Modulation Control of T12 related Outputs For each of the six T12 related output lines represented by x in the Figure 14 11 T12MODENx enables t...

Page 368: ...put signal COUT63_T13_o is the output signal that is configured by COUT63PS and the enable bit ECT13O with the trap functionality The output level of the passive state is selected by bit PSL63 Figure...

Page 369: ...gnal becomes active and the trap function is enabled by bit TRPPEN It can also be entered by software by setting bit TRPF trap input flag thus leading to TRPS 1 trap state indication flag The trap sta...

Page 370: ...1 3 2010 02 CCU6 V 1 0 synchronized to T13 PWM after TRPF is reset T13 period match no synchronization to T12 or T13 Figure 14 14 Trap State Synchronization with TRPM2 0 CTRAP active T12 T13 sync to T...

Page 371: ...account by the hardware at a well defined moment and synchronized to a PWM period This avoids unintended pulses due to unsynchronized modulation sources T12 T13 SW Figure 14 15 Modulation Selection an...

Page 372: ...et during the write action to the register the flag R is automatically set By using this the update takes place completely under software control A shadow transfer interrupt can be generated when the...

Page 373: ...be implemented to suppress spikes on the Hall inputs In case of a Hall event the DTC0 is reloaded and it starts counting and generates a delay between the detected event and the sampling point After...

Page 374: ...he T12 count value is captured to channel 0 representing the actual motor speed and the T12 is reset When the timer reaches the compare value in channel 1 the next multi channel state is switched by t...

Page 375: ...ctive inactive 1 1 0 inactive active inactive active inactive inactive 0 1 0 inactive active inactive inactive inactive active 0 1 1 active inactive inactive inactive inactive active 0 0 1 active inac...

Page 376: ...re 14 17 Block Commutation in Rotate Left Mode Figure 14 18 Block Commutation in Rotate Right Mode 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 CCPOS0 CCPOS1 CCPOS2 CC60 CC61 CC62 COUT60 COUT61 COUT62 1 1 1 1...

Page 377: ...pendently of the interrupt flag in register IS Register IS can only be read write actions have no impact on the contents of this register The software can set or reset the bits individually by writing...

Page 378: ...it CCU_DIS in register PMCON1 as described below Refer to Chapter 8 1 4 for details on peripheral clock management PMCON1 Power Mode Control Register 1 Reset Value 00H 7 6 5 4 3 2 1 0 0 CDC_DIS CAN_DI...

Page 379: ...dule suspend bits T12SUSP and T13SUSP in SFR MODSUSP MODSUSP Module Suspend Control Register Reset Value 01H 7 6 5 4 3 2 1 0 0 T21SUSP T2SUSP T13SUSP T12SUSP WDTSUSP r rw rw rw rw rw Field Bits Typ De...

Page 380: ...STRP 11B P4_DIR P7 0 Input P2 0 CCPOS0_0 ISPOS0 00B P2_DIR P0 0 Input P1 5 CCPOS0_1 ISPOS0 01B P1_DIR P5 0 Input P3 1 CCPOS0_2 ISPOS0 10B P3_DIR P1 0 Input P4 4 CCPOS0_3 ISPOS0 11B P4_DIR P4 0 Input P...

Page 381: ...C61 01B P0_DIR P0 0 Input P0_DIR P0 1 Output P0_ALTSEL0 P0 0 P0_ALTSEL1 P0 1 P3 1 CC61_2 ISCC61 10B P3_DIR P1 0 Input P3_DIR P1 1 Output P3_ALTSEL0 P1 0 P3_ALTSEL1 P1 1 P2 0 CC61_3 ISCC61 11B P2_DIR P...

Page 382: ...62_2 P4_DIR P6 1 Output P4_ALTSEL0 P6 1 P4_ALTSEL1 P6 0 P2 1 CC62_3 ISCC62 11B P2_DIR P1 0 Input P3 5 COUT62_0 P3_DIR P5 1 Output P3_ALTSEL0 P5 1 P3_ALTSEL1 P5 0 P0 5 COUT62_1 P0_DIR P5 1 Output P0_AL...

Page 383: ...IST12HR 00B P1_DIR P6 0 Input P0 0 T12HR_1 IST12HR 01B P0_DIR P0 0 Input P2 0 T12HR_2 IST12HR 10B P2_DIR P0 0 Input P1 7 T13HR_0 IST13HR 00B P1_DIR P7 0 Input P0 1 T13HR_1 IST13HR 01B P0_DIR P1 0 Inpu...

Page 384: ..._CC63SRL The addresses non mapped of the kernel SFRs are listed in Table 14 3 Table 14 3 SFR Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 9AH CC63SRL CC63RL T12MSELL MCMOUTL 9BH CC63...

Page 385: ...d the value indicates the currently active page addr y x 1 STNR 5 4 w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP If OP 10B the...

Page 386: ...g The value written to the bit positions of PAGE is stored In parallel the previous contents of PAGE are saved in the storage bit field STx indicated by STNR 11 Automatic restore page action The value...

Page 387: ...T12L Timer T12 Counter Register Low Page 14 46 T12H Timer T12 Counter Register High Page 14 46 T12PRL Timer T12 Period Register Low Page 14 47 T12PRH Timer T12 Period Register High Page 14 47 CC6xRL...

Page 388: ...ge 14 62 TCTR2H Timer Control Register 2 High Page 14 64 TCTR4L Timer Control Register 4 Low Page 14 65 TCTR4H Timer Control Register 4 High Page 14 66 Modulation Control Registers MODCTRL Modulation...

Page 389: ...ter High Page 14 80 ISSL Capture Compare Interrupt Status Set Register Low Page 14 83 ISSH Capture Compare Interrupt Status Set Register High Page 14 84 ISRL Capture Compare Interrupt Status Reset Reg...

Page 390: ...C61_0 01 The input pin for CC61_1 10 The input pin for CC61_2 11 The input pin for CC61_3 ISCC62 5 4 rw Input Select for CC62 This bit field defines the port pin that is used for the CC62 capture inpu...

Page 391: ...nal 00 The input pin for CCPOS1_0 01 The input pin for CCPOS1_1 10 The input pin for CCPOS1_2 11 The input pin for CCPOS1_3 ISPOS2 5 4 rw Input Select for CCPOS2 This bit field defines the port pin th...

Page 392: ...ture compare modes selectable Refer to the following register description for the selection Field Bits Type Description IST13HR 1 0 rw Input Select for T13HR This bit field defines the port pin that i...

Page 393: ...late The value 1000B must be programmed to MSEL0 MSEL1 and MSEL2 if the hall signals are used In this mode the contents of timer T12 are captured in CC60 and T12 is reset after the detection of a val...

Page 394: ...6nR after a falling edge at the input pin CC6n The timer value of T12 is stored in CC6nSR after a falling edge at the input pin CCPOSx 1110 The timer value of T12 is stored in CC6nR after any edge at...

Page 395: ...ed pins CC6n and COUT6n can be used for I O No capture action 0001 Compare output on pin CC6n pin COUT6n can be used for I O No capture action 0010 Compare output on pin COUT6n pin CC6n can be used fo...

Page 396: ...e operation according to 0000 Compare outputs disabled pins CC6n and COUT6n can be used for I O No capture action 0001 Compare output on pin CC6n pin COUT6n can be used for I O No capture action 0010...

Page 397: ...n bit fields In all modes a trigger by software by writing a 1 to bit SWHC is possible 000 Any edge at one of the inputs CCPOSx x 0 1 2 triggers the sampling 001 A T13 compare match triggers the sampl...

Page 398: ...ible timings and delays T12L Timer T12 Counter Register Low Reset Value 00H 7 6 5 4 3 2 1 0 T12CVL rwh Field Bits Type Description T12CVL 7 0 rwh Timer T12 Counter Value Low Byte This register represe...

Page 399: ...On reaching this value the timer T12 is set to zero edge aligned mode or changes its count direction to down counting center aligned mode T12PRH Timer T12 Period Register High Reset Value 00H 7 6 5 4...

Page 400: ...lue In capture mode the captured value of T12 can be read from these registers CC6xRH x 0 1 2 Capture Compare Register for Channel CC6x High Reset Value 00H 7 6 5 4 3 2 1 0 CC6xVH x 0 1 2 rh Field Bit...

Page 401: ...fer In capture mode the captured value of T12 can be read from these registers CC6xSRH x 0 1 2 Capture Compare Shadow Register for Channel CC6x High Reset Value 00H 7 6 5 4 3 2 1 0 CC6xSH x 0 1 2 rwh...

Page 402: ...trol Register for Timer T12 High Reset Value 00H 7 6 5 4 3 2 1 0 0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0 r rh rh rh r rw rw rw Field Bits Type Description DTEx x 0 1 2 2 0 rw Dead Time Enable Bits Bits DTE0...

Page 403: ...signal T13 can be synchronized to several timer T12 events Timer T13 supports only compare mode on its compare channel CC63 Register T13 represents the counting value of timer T13 It can only be writt...

Page 404: ...value of timer T13 T13H Timer T13 Counter Register High Reset Value 00H 7 6 5 4 3 2 1 0 T13CVH rwh Field Bits Type Description T13CVH 7 0 rwh Timer T13 Counter Value High Byte This register represents...

Page 405: ...he counter value for T13 which leads to a period match On reaching this value the timer T13 is set to zero CC63RL Capture Compare Register for Channel CC63 Low Reset Value 00H 7 6 5 4 3 2 1 0 CC63VL r...

Page 406: ...6 5 4 3 2 1 0 CC63SL rw Field Bits Type Description CC63SL 7 0 rw Shadow Register for Channel CC63 Compare Value Low Byte The contents of bit field CC63S are transferred to the bit field CC63V during...

Page 407: ...are related to T12 bit CC63ST is related to T13 0 In compare mode the timer count is less than the compare value In capture mode the selected edge has not yet been detected since the bit has been res...

Page 408: ...driven by the output pin Bits CC6xPS COUT6xPS x 0 1 2 are related to T12 bit COUT63PS is related to T13 0 The corresponding compare output drives passive level while CC6xST is 0 1 The corresponding c...

Page 409: ...rresponding CC6xST bits by software This feature allows the user to individually change the status of the output lines by software e g when the corresponding compare timer is stopped This allows a bit...

Page 410: ...eset These bits are used to reset the corresponding CC6xST bits by software This feature allows the user to individually change the status of the output lines by software e g when the corresponding co...

Page 411: ...6 101 fT12 fCCU 32 110 fT12 fCCU 64 111 fT12 fCCU 128 T12PRE 3 rw Timer T12 Prescaler Bit In order to support higher clock frequencies an additional prescaler factor of 1 256 can be enabled for the pr...

Page 412: ...while counting up or a one match while counting down 0 The shadow register transfer is disabled 1 The shadow register transfer is enabled CDIR 6 rh Count Direction of Timer T12 This bit is set reset...

Page 413: ...led T13R 4 rh Timer T13 Run Bit T13R starts and stops timer T13 It is set reset by software by setting bits T13RS or T13RR or it is set reset by hardware according to the function defined by bit field...

Page 414: ...ents with a programmable delay after well defined PWM actions of T12 For example this feature can be used to trigger AD conversions after a specified delay to avoid problems due to switching noise syn...

Page 415: ...13 automatic set of T13R for synchronization to T12 compare signals according to following combinations 000 no action 001 set T13R on a T12 compare event on channel 0 010 set T13R on a T12 compare eve...

Page 416: ...0 rw Timer T12 External Run Selection Bit field T12RSEL defines the event of signal T12HR that can set the run bit T12R by hardware 00 The external setting of T12R is disabled 01 Bit T12R is set if a...

Page 417: ...0 T12R is not influenced 1 T12R is cleared T12 stops counting T12RS 1 w Timer T12 Run Set Setting this bit sets the T12R bit 0 T12R is not influenced 1 T12R is set T12 counts T12RES 2 w Timer T12 Res...

Page 418: ...13RS 1 w Timer T13 Run Set Setting this bit sets the T13R bit 0 T13R is not influenced 1 T13R is set T13 counts T13RES 2 w Timer T13 Reset 0 No effect on T13 1 The T13 counter register is reset to zer...

Page 419: ...Modulation Control Register Low Reset Value 00H 7 6 5 4 3 2 1 0 MCMEN 0 T12MODEN rw r rw Field Bits Type Description T12MODEN 5 0 rw T12 Modulation Enable Setting these bits enables the modulation of...

Page 420: ...13O 0 T13MODEN rw r rw Field Bits Type Description T13MODEN 5 0 rw T13 Modulation Enable Setting these bits enables the modulation of the corresponding compare channel by a PWM pattern generated by ti...

Page 421: ...in which is monitored inverted level by bit TRPF in register IS While TRPF 1 trap input active the trap state bit TRPS in register IS is set to 1 ECT13O 7 rw Enable Compare Timer T13 Output 0 The alte...

Page 422: ...is detected synchronization to T13 10 reserved 11 The trap state is left return to normal operation according to TRPM2 immediately without any synchronization to T12 or T13 TRPM2 2 rw Trap Mode Contro...

Page 423: ...UT61 Bit 4 trap functionality of CC62 Bit 5 trap functionality of COUT62 The enable feature of the trap functionality is defined as follows 0 The trap functionality of the corresponding output signal...

Page 424: ...led A trap can only be generated by software by setting bit TRPF 1 The trap functionality based on the input pin CTRAP is enabled A trap can be generated by software by setting bit TRPF or by CTRAP 0...

Page 425: ...olling the output states for multi channel mode Furthermore the appropriate signals for the block commutation by Hall sensors can be selected This register is a shadow register that can be written for...

Page 426: ...is updated by the value written to bit field MCMPS 0 6 r Reserved Returns 0 if read should be written with 0 MCMOUTSH Multi Channel Mode Output Shadow Register High Reset Value 00H 7 6 5 4 3 2 1 0 STR...

Page 427: ...fields CURHS and EXPHS This functionality permits an update triggered by software When read this bit always delivers 0 0 The bit fields CURH and EXPH are updated according to the defined hardware act...

Page 428: ...OUT62 The multi channel patterns can set the related output to the passive state 0 The output is set to the passive state The PWM generated by T12 or T13 is not taken into account 1 The output can del...

Page 429: ...r a wrong pattern If the current hall pattern at the hall input pins is equal to the bit field EXPH bit CHE correct hall event is set and an interrupt request is generated if enabled by bit ENCHE If t...

Page 430: ...for the shadow transfer from MCMPS to MCMP The trigger request is stored in the reminder flag R until the shadow transfer is done and flag R is cleared automatically with the shadow transfer The shado...

Page 431: ...nsfer 01 T13 zero match triggers the shadow transfer 10 a T12 zero match while counting up triggers the shadow transfer 11 reserved no action 0 3 6 7 r Reserved Returns 0 if read should be written wit...

Page 432: ...ince this bit has been reset for the last time 1 A timer T12 one match while counting down has been detected T12PM 7 rh Timer T12 Period Match Flag 0 A timer T12 period match while counting up has not...

Page 433: ...tware TRPS 3 rh Trap State 0 The trap state is not active 1 The trap state is active Bit TRPS is set while bit TRPF 1 It is reset according to the mode selected in register TRPCTR During the trap stat...

Page 434: ...he individual interrupt request set bits required to generate a CCU6 interrupt request by software WHE 5 rh Wrong Hall Event On every valid hall edge the contents of EXPH are compared with the pattern...

Page 435: ...C60F 1 w Set Capture Compare Match Falling Edge Flag 0 No action 1 Bit ICC60F in register IS will be set SCC61R 2 w Set Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS w...

Page 436: ...No action 1 Bit T13CM in register IS will be set ST13PM 1 w Set Timer T13 Period Match Flag 0 No action 1 Bit T13PM in register IS will be set STRPF 2 w Set Trap Flag 0 No action 1 Bits TRPF and TRPS...

Page 437: ...ICC60F in register IS will be reset RCC61R 2 w Reset Capture Compare Match Rising Edge Flag 0 No action 1 Bit ICC61R in register IS will be reset RCC61F 3 w Reset Capture Compare Match Falling Edge Fl...

Page 438: ...eriod Match Flag 0 No action 1 Bit T13PM in register IS will be reset RTRPF 2 w Reset Trap Flag 0 No action 1 Bit TRPF in register IS will be reset not taken into account while input CTRAP 0 and TRPPE...

Page 439: ...curs The interrupt line that will be activated is selected by bit field INPCC60 ENCC60F 1 rw Capture Compare Match Falling Edge Interrupt Enable for Channel 0 0 No interrupt will be generated if the s...

Page 440: ...rw Capture Compare Match Falling Edge Interrupt Enable for Channel 2 0 No interrupt will be generated if the set condition for bit ICC62F in register IS occurs 1 An interrupt will be generated if the...

Page 441: ...rrupt will be generated if the set condition for bit T13PM in register IS occurs 1 An interrupt will be generated if the set condition for bit T13PM in register IS occurs The interrupt line that will...

Page 442: ...ng the idle state the bit field MCMP is automatically cleared 0 The bit IDLE is not automatically set when a wrong hall event is detected 1 The bit IDLE is automatically set when a wrong hall event is...

Page 443: ...Interrupt output line SR0 is selected 01 Interrupt output line SR1 is selected 10 Interrupt output line SR2 is selected 11 Interrupt output line SR3 is selected INPCC62 5 4 rw Interrupt Node Pointer f...

Page 444: ...errupt Node Pointer for Timer T12 Interrupts This bit field defines the interrupt output line which is activated due to a set condition for bit T12OM if enabled by bit ENT12OM or for bit T12PM if enab...

Page 445: ...een the CAN nodes or to setup a FIFO buffer The message objects are organized in double chained lists where each CAN node has its own list of message objects A CAN node stores frames only into message...

Page 446: ...ames Message objects can be grouped into four priority classes for transmission and reception The selection of the message to be transmitted first can be based on frame identifier IDE bit and RTR bit...

Page 447: ...V1 3 2010 02 MultiCAN V1 0 Up to 8 interrupt output lines are available Interrupt requests can be individually routed to one of the 8 interrupt output lines Message post processing notifications can b...

Page 448: ...cessing according to the ISO 11898 standard This includes conversion between the serial data stream and the input output registers Bit Timing Unit The Bit Timing Unit defines the length of a bit time...

Page 449: ...received CAN frame Transmit acceptance filtering to determine the message object to be transmitted first individually for each CAN node Transfer contents between message objects and the CAN nodes taki...

Page 450: ...source is connected to the same interrupt node pointer in the interrupt node pointer register the requests are combined to one common line Figure 15 3 General Interrupt Structure MultiCAN_int_struct I...

Page 451: ...r a maximum of 500 kbit s 50 of the indicated value are required The values imply that the CPU executes maximum access to the MultiCAN module The values may contain rounding effects Table 15 1 Minimum...

Page 452: ...and receiver time base The Synchronization Segment length is always one tq The Propagation Time Segment TProp takes into account the physical propagation delay in the transmitter output driver on the...

Page 453: ...field NBTRx SJW The maximum relative tolerance for fCAN depends on the Phase Buffer Segments and the re synchronization jump width A valid CAN bit timing must be written to the register NBTR before re...

Page 454: ...the fault confinement of the CAN device Its two counters the Receive Error Counter NECNTx REC and the Transmit Error Counter NECNTx TEC are incremented and decremented by commands from the Bit Stream...

Page 455: ...e starts the value of the frame counter is captured and stored to the bit field NFCRx CFC After the successful transfer of the frame the captured value is copied to the bit field MOIPRn CFCVAL of the...

Page 456: ...ts MultiCAN_Can_interrupts TRIE TRINP TXOK RXOK Receive Transmit Correct Message Object Transfer 1 LECIE LECINP LEC CAN Error EWRN BOFF 1 ALINP ALIE ALERT LLE LOE List Length Error List Object Error C...

Page 457: ...and bit field LIST END points to the last element in the list object 3 in the example The number of elements in the list is indicated by bit field LIST SIZE SIZE number of list elements 1 thus SIZE 2...

Page 458: ...ated message objects is ordered by message number predecessor of message object n is object n 1 successor of object n is object n 1 15 1 4 3 Connection to the CAN Nodes Each CAN node is linked to one...

Page 459: ...roller The list controller basically serves two purposes 1 Ensure that all operations that modify the list structure result in a consistent list structure 2 Present flexibility to the user The list co...

Page 460: ...ch message object The end of this CAN RAM initialization is indicated by bit PANCTR BUSY becoming inactive In case of a dynamic allocation command that takes an element from the list of unallocated ob...

Page 461: ...allocation process by one access cycle As soon as the command is finished the BUSY flag becomes inactive BUSY 0 and write accesses to the Panel Control Register are enabled again Additionally the No O...

Page 462: ...sage object functionality is available but no transmit request will be executed 15 1 5 2 Loop Back Mode The MultiCAN module provides a loop back mode to enable an in system test of the MultiCAN module...

Page 463: ...measurement results are written into the NFCRx CFC bit field Whenever NFCRx CFC is updated in bit timing analysis mode the bit NFCRx CFCOV is set to indicate the CFC update event If NFCRx CFCIE is se...

Page 464: ...edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points Synchronization analysis can be used for example for fine tuning of the bau...

Page 465: ...ntifier If bit MOAMRn MIDE 0 the IDE bit of the received frame is don t care In this case message objects with standard and extended frames are accepted The identifier of the received frame matches th...

Page 466: ...object b MOb are two message objects qualified for transmission MOb is a list successor of MOa This means MOb can be reached by means of successively stepping forward in the list starting from a If bo...

Page 467: ...errupt can be generated and routed to one of the eight CAN interrupt output lines see Figure 15 9 A receive interrupt occurs also after a frame storage event has been induced by a FIFO or a gateway ac...

Page 468: ...sage Interrupt Request Routing MultiCAN_msg_interrupts TXIE TXINP TXPND Message n received Message n transmitted RXINP MOSTATn MOFCRn MOIPRn MOIPRn Message n FIFO full OVIE RXIE RXPND MMC 1 0001B 0010...

Page 469: ...with 32 pending bits available to each resulting in 64 pending bits Figure 15 10 shows the allocation of the message pending bits Figure 15 10 Message Pending Bit Allocation MultiCAN_msgpnd 7 6 5 4 3...

Page 470: ...ending bits are used in receive and transmit cases If MPSEL 1111B the location selection operates in the following way At a transmit event the bit 1 of TXINP define the number k of a Pending Register...

Page 471: ...receive acceptance filtering 2 The CPU clears MSGVAL to re configure the message object 3 The CPU sets MSGVAL again after re configuration 4 The end of the received frame is reached As MSGVAL is set t...

Page 472: ...o longer wins receive acceptance filtering RXUPD NEWDAT and MSGLST An ongoing frame storage process is indicated by the bit MOSTATn RXUPD Receive Updating RXUPD is set with the start and cleared with...

Page 473: ...c successful M SGVAL RTSEL 1 NEW DAT 1 NEW DAT 1 RXUPD 0 RXPND 1 M SGLST 1 DIR 1 TXRQ 1inthis or inforeignobj Get Datafrom gateway fifo source Start receiving CANfram e Done Done Done Done Copy Fram e...

Page 474: ...Table 15 3 Message Transmission Bit Definitions Bit Description MSGVAL Message Valid This is the main switch bit of the message object TXRQ Transmit Request This is the standard transmit request bit T...

Page 475: ...learing TXRQ time stamp update message interrupt etc within the old context of the object can occur after the message object becomes valid again but within a new context NEWDAT When the content of a m...

Page 476: ...nsm it acc filtering Done no yes yes 1 tim em ilestones Copy M essagetointernal transm it buffer M SGVAL TXRQ TXEN0 TXEN1 1 continously duringm essage copying Request Transm issionof internal buffer o...

Page 477: ...and is replaced with the content of the new received message indicated by MSGLST 1 In single data transfer mode SDT 1 bit MSGVAL of the message object is automatically cleared by hardware after the st...

Page 478: ...ted to the same list as the slave objects Only the slave object must be allocated to a common list as they are chained together Several pointers BOT CUR and TOP that are located in the Register MOFGPR...

Page 479: ...es to be detected or to issue a warning interrupt when the FIFO becomes full Figure 15 13 FIFO Structure with FIFO Base Object and n FIFO Slave Objects MultiCAN_msgobj_fifo Slave Object fi PPREV f i 1...

Page 480: ...implicitly assumed for the FIFO slave object and a standard message delivery is performed The actual message mode MMC setting of the FIFO slave object is ignored For the slave object no acceptance fi...

Page 481: ...GVAL 1 first Before a Transmit FIFO becomes de installed during operation its slave objects must be tagged invalid MSGVAL 0 The Transmit FIFO uses the bit MOCTRn TXEN1 of all FIFO elements to select t...

Page 482: ...copied from the gateway source object to the gateway destination object 2 If bit MOFCRs IDC is set the identifier MOARs ID and the identifier extension MOARs IDE are copied from the gateway source ob...

Page 483: ...reception of remote frames source object is transmit object Figure 15 14 Gateway Transfer from Source to Destination MultiCAN_Msgobj_gateway Copy if IDCSource 1 Pointer to Destination Message Object...

Page 484: ...are two capabilities to handle remote requests that appear on the destination side assuming that the source object is a receive object and the destination is a transmit object i e DIRsource 0 and DIR...

Page 485: ...by configuring the register bits Vn n 3 0 in the register CAN_ADCON Only the valid data bytes are sent during the write process The register bits Vn n 3 0 has no effect on the read process During the...

Page 486: ...ecome 1 When Register bit BSY becomes 0 the transmission is finished Read Process to the MultiCAN Kernel Write the address of the MultiCAN kernel register to the CAN_ADL and CAN_ADH registers Write th...

Page 487: ...4 CAN I O Control Selection Port Lines PISEL Register Bit Input Output Control Register Bits I O P1 0 RXDC0_0 NPCR0 RXSEL 000B P1_DIR P0 0B Input P1 1 TXDC0_0 P1_DIR P1 1B Output P1_ALTSEL0 P1 1B P1_...

Page 488: ..._DIR P3 1B Output P3_ALTSEL0 P3 1B P3_ALTSEL1 P3 1B P1 4 RXDC1_3 NPCR1 RXSEL 011B P1_DIR P4 0B Input P1 3 TXDC1_3 P1_DIR P3 1B Output P1_ALTSEL0 P3 1B P1_ALTSEL1 P3 1B PMCON1 Power Mode Control Regist...

Page 489: ...54 MSPNDk Message Pending Register k 0120H k x 4H Page 15 56 MSIDk Message Index Register k 0140H k x 4H Page 15 57 MSIMASK Message Index Mask Register 01C0H Page 15 58 PANCTR Panel Control Register...

Page 490: ...ARn Message Object n Arbitration Register 1018H n x 20H Page 15 92 MOCTRn MOSTATn Message Object n Control Reg Message Object n Status Reg 101CH n x 20H Page 15 76 Page 15 79 1 The following ranges fo...

Page 491: ...NO Node x 1 0 Node x Interrupt Ptr Reg Node x Port Control Reg Node x Bit Timing Reg Node x Error Counter Reg Node x Frame Counter Reg 300H Node 1 Registers NOBASE 00H Message Object Registers MO n F...

Page 492: ...lue 0000 0301H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PANAR2 PANAR1 rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RBU SY BUS Y PANCMD r rh rh rwh Field Bits Type Description PANCMD 7 0 rwh...

Page 493: ...iption 00H No Operation Writing 00H to PANCMD has no effect No new command is started 01H Result Bit 7 ERR Bit 6 0 undefined Initialize Lists Run the initialization sequence to reset the CTRL and LIST...

Page 494: ...the first message object of the list of unallocated objects to the selected list The message object is appended to the end of the list The message number of the message object is returned in PANAR1 A...

Page 495: ...Number Static Insert Behind Remove a message object source object from the list that it currently belongs to and insert it behind a given destination object into the list structure of the destination...

Page 496: ...28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPSEL 0 rw r Field Bits Type Description MPSEL 15 12 rw Message Pending Selector Bit field MPSEL allows the bit positi...

Page 497: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 IT r w Field Bits Type Description IT 7 0 w Interrupt Trigger Writing a 1 to IT n n 0 7 generates an interrupt r...

Page 498: ...e 1 LIST 7 3 are not associated to a CAN node free lists LIST0 List Register 0 Reset Value 001F 1F00H LISTm m 1 7 List Register m Reset Value 0100 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 499: ...XC886 888CLM Controller Area Network MultiCAN Controller User s Manual 15 55 V1 3 2010 02 MultiCAN V1 0 0 31 25 r Reserved ead as 0 should be written with 0 Field Bits Type Description...

Page 500: ...ism is implemented in the MultiCAN module to select the highest priority object within a collection of message objects The Message Pending Register MSPNDk contains the pending interrupt notification o...

Page 501: ...20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 INDEX r rh Field Bits Type Description INDEX 5 0 rh Message Pending Index The value of INDEX is given by the bit position i of the pending b...

Page 502: ...ster is used commonly for all Message Pending registers and their associated Message Index registers MSIMASK Message Index Mask Register Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 503: ...n information that is directly related to the operation of the CAN nodes and are shared among the nodes The Node Control Register NCRx contains basic settings that define the operation of the CAN node...

Page 504: ...s node in the CAN traffic Any ongoing frame transfer is cancelled and the transmit line goes recessive If the CAN node is in the bus off state then the running bus off recovery sequence is continued I...

Page 505: ...abled 1 Alert interrupt is enabled Bit field NIPRx ALINP selects the interrupt output line which becomes activated at this type of interrupt CANDIS 4 rw CAN Disable Setting this bit disables the CAN n...

Page 506: ...XC886 888CLM Controller Area Network MultiCAN Controller User s Manual 15 62 V1 3 2010 02 MultiCAN V1 0 0 31 8 5 r Reserved Read as 0 should be written with 0 Field Bits Type Description...

Page 507: ...cription LEC 2 0 rwh Last Error Code This bit field indicates the type of the last most recent CAN error The encoding of this bit field is described in Table 15 8 TXOK 3 rwh Message Transmitted Succes...

Page 508: ...warning limit NECNTx EWRNLVL BOFF 7 rh Bus off Status 0 CAN controller is not in the bus off state 1 CAN controller is in the bus off state LLE 8 rwh List Length Error 0 No List Length Error since la...

Page 509: ...ransmission the CAN node tried to send a recessive level 1 outside the arbitration field and the acknowledge slot but the monitored bus value was dominant 101B Bit0 Error Two different conditions are...

Page 510: ...NP TRINP LECINP ALINP rw rw rw rw Field Bits Type Description ALINP 3 0 rw Alert Interrupt Node Pointer ALINP selects the interrupt output line CANSRCm m 0 7 for an alert interrupt of CAN Node x 0000B...

Page 511: ...pt output line CANSRC1 is selected 0111B Interrupt output line CANSRC7 is selected 1000B 1111BIReserved CFCINP 15 12 rw Frame Counter Interrupt Node Pointer CFCINP selects the interrupt output line CA...

Page 512: ...n RXSEL 2 0 rw Receive Select RXSEL selects one out of 8 possible receive inputs The CAN receive signal is performed only through the selected input Note In XC886 888 only specific combinations of RXS...

Page 513: ...8 0 The duration of one time quantum is given by 8 BRP 1 clock cycles if DIV8 1 SJW 7 6 rw Re Synchronization Jump Width SJW 1 time quanta are allowed for re synchronization TSEG1 11 8 rw Time Segment...

Page 514: ...r User s Manual 15 70 V1 3 2010 02 MultiCAN V1 0 DIV8 15 rw Divide Prescaler Clock by 8 0 A time quantum lasts BRP 1 clock cycles 1 A time quantum lasts 8 BRP 1 clock cycles 0 31 16 r Reserved Read as...

Page 515: ...e Error Counter Bit field REC contains the value of the receive error counter of CAN node x TEC 15 8 rwh Transmit Error Counter Bit field TEC contains the value of the transmit error counter of CAN no...

Page 516: ...rwh rw r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFC rwh Field Bits Type Description CFC 15 0 rwh CAN Frame Counter In Frame Count Mode CFMOD 00B this bit field contains the frame count value In...

Page 517: ...ed during the SOF bit of a new frame The sampled value is visible in the CFC field Bit Timing Mode The available bit timing measurement modes are shown in Table 15 9 If CFCIE is set then an interrupt...

Page 518: ...s monitored on the receive input the time measured in clock cycles between this edge and the most recent dominant edge is stored in CFC 010B Whenever a dominant edge is received as a result of a trans...

Page 519: ...ansmit only RTR reserved bits IDE DLC MSB bit 7 MSB in each data byte and the first bit of the ID extension 10B Bit This code represents a bit inside a frame segment with a length of more than one bit...

Page 520: ...22 21 20 19 18 17 16 0 SET DIR SET TXE N1 SET TXE N0 SET TXR Q SET RXE N SET RTS EL SET MSG VAL SET MSG LST SET NEW DAT SET RXU PD SET TXP ND SET RXP ND w w w w w w w w w w w w w 15 14 13 12 11 10 9...

Page 521: ...on for RXEN see Table 15 11 RESTXRQ SETTXRQ 8 24 w w Reset Set Transmit Request These bits control the set reset condition for TXRQ see Table 15 11 RESTXEN0 SETTXEN0 9 25 w w Reset Set Transmit Enable...

Page 522: ...010 02 MultiCAN V1 0 Write 1 Write 0 Reset element No write Write 0 Write 1 Set element No write 1 The parameter y stands for the second part of the bit name RXPND TXPND up to DIR Table 15 11 Reset Se...

Page 523: ...Value n 1 01000000H n 1 00010000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PNEXT PPREV rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LIST DIR TX EN1 TX EN0 TX RQ RX EN RTS EL MSG VAL MSG LST NEW...

Page 524: ...s been stored in message object n NEWDAT is cleared by hardware when a CAN transmission of message object n has been started NEWDAT should be set by software after the new transmit data has been store...

Page 525: ...rame Transmission RTSEL is set by hardware when message object n has been identified to be transmitted next It is checked that RTSEL is still set before message object n is actually set up for transmi...

Page 526: ...ware TXEN0 9 rh Transmit Enable 0 0 Message object n is not enabled for frame transmission 1 Message object n is enabled for frame transmission Message object n can be transmitted only if both bits TX...

Page 527: ...h List Allocation LIST indicates the number of the message list to which message object n is allocated LIST is updated by hardware when the list allocation of the object is modified by a panel command...

Page 528: ...CANSRCm m 0 7 for a receive interrupt event of message object n RXINP can also be taken for message pending bit selection see Page 15 25 0000B Interrupt output line CANSRC0 is selected 0001B Interrupt...

Page 529: ...cts the bit position of the bit in the Message Pending Register that is set upon a message object n receive transmit interrupt CFCVAL 31 16 rwh CAN Frame Counter Value When a message is stored in mess...

Page 530: ...w rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DAT C DLC C IDC GDF S 0 MMC rw rw rw rw rw rw rw Field Bits Type Description MMC 3 0 rw Message Mode Control MMC controls the message mode of message ob...

Page 531: ...le only to a gateway source object ignored in other nodes DATC 11 rw Data Copy 0 Data fields are not copied 1 Data fields in registers MODATALn and MODATAHn of the gateway source object after storing...

Page 532: ...of SEL in the FIFO Gateway Pointer Register 0 FIFO full interrupt is disabled 1 FIFO full interrupt is enabled If message object n is a Receive FIFO base object bit field MOIPRn TXINP selects the inte...

Page 533: ...part in a successful data transfer receive or transmit If SDT 1 and message object n is a FIFO base object then MSGVAL is reset when the pointer to the current object CUR reaches the value of SEL in t...

Page 534: ...points to the first element in a FIFO structure TOP 15 8 rw Top Pointer Bit field TOP points to the last element in a FIFO structure CUR 23 16 rwh Current Object Pointer Bit field CUR points to the ac...

Page 535: ...2 11 10 9 8 7 6 5 4 3 2 1 0 AM rw Field Bits Type Description AM 28 0 rw Acceptance Mask for Message Identifier Bit field AM is the 29 bit mask for filtering incoming messages with standard identifier...

Page 536: ...6 25 24 23 22 21 20 19 18 17 16 PRI IDE ID rw rwh rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID rwh Field Bits Type Description ID 28 0 rwh CAN Identifier of Message Object n Identifier of a standard m...

Page 537: ...class PRI also determines the acceptance filtering method for transmission 00B Reserved 01B Transmit acceptance filtering is based on the list order This means that message object n is considered for...

Page 538: ...Frame B MOAR IDE 1 send Extended Frame Standard Frames have higher transmit priority than Extended Frames with equal standard identifier A MOAR 28 18 B MOAR 28 18 A MOAR IDE B MOAR IDE 0 A MOCTR DIR 1...

Page 539: ...n reception and ignored for transmission MODATALn n 0 31 Message Object n Data Register Low Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB3 DB2 rwh rwh 15 14 13 12 11 10 9 8...

Page 540: ...n reception and ignored for transmission MODATAHn n 0 31 Message Object n Data Register High Reset Value 0000 0000H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB7 DB6 rwh rwh 15 14 13 12 11 10 9...

Page 541: ...mission is in progress AUAD 3 2 rw Auto Increment Decrement the Address 00 No increment decrement the address 01 Auto increment the current address 1 10 Auto decrement the current address 1 11 Auto in...

Page 542: ...et Value 0000 0000B 7 6 5 4 3 2 1 0 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 rwh Field Bits Type Description CAn n 2 to 9 n 2 rwh CAN Address Bit n CAN_ADH CAN Address Register High Reset Value 0000 0000B 7 6...

Page 543: ...7 6 5 4 3 2 1 0 CD 7 0 rwh Field Bits Type Description CD 7 0 rwh CAN Data Byte 0 CAN_DATA1 CAN Data Register 1 Reset Value 0000 0000B 7 6 5 4 3 2 1 0 CD 15 8 rwh Field Bits Type Description CD 7 0 r...

Page 544: ...er Area Network MultiCAN Controller User s Manual 15 100 V1 3 2010 02 MultiCAN V1 0 CAN_DATA3 CAN Data Register 3 Reset Value 0000 0000B 7 6 5 4 3 2 1 0 CD 31 24 rwh Field Bits Type Description CD 7 0...

Page 545: ...2 LSB respectively Eight analog channels Four independent result registers Result data protection for slow CPU access wait for read mode Single conversion mode Autoscan functionality Limit checking f...

Page 546: ...erating the conversion result The digital part defines and controls the overall functionality of the ADC module and includes Digital data and conversion request handling for controlling the conversion...

Page 547: ...he digital part This clock is used for the arbiter defines the duration of an arbitration round and other digital control structures e g registers and the interrupt generation The internal clock for t...

Page 548: ...conversion error could increase due to loss of charges on the capacitors if fADC becomes too low during slow down mode 16 2 1 Conversion Timing The analog to digital conversion procedure consists of t...

Page 549: ...is common to all analog input channels and is controlled by bit field STC in register INPCR0 tS 2 STC tADCI 16 1 Conversion Phase During the conversion phase the analog voltage is converted into an 8...

Page 550: ...e synchronizing sampling charge redistribution tCONV is given by tCONV tADC 1 r 3 n STC 16 2 where r CTC 2 for CTC 00B 01B or 10B r 32 for CTC 11B CTC Conversion Time Control STC Sample Time Control n...

Page 551: ...tely 100 ns Refer to Section 16 7 1 for register description of disabling the ADC analog part If the ADC functionality is not required at all it can be completely disabled by gating off its clock inpu...

Page 552: ...behavior of each analog input such as the interrupt behavior a pointer to a result register a pointer to a channel class etc An input class register that delivers general channel control information s...

Page 553: ...all arbitration slots is called an arbitration round An arbitration slot must be enabled ASENx 1 before it can take part in the arbitration Each request source has a source priority that can be progra...

Page 554: ...CSMx x 0 1 Wait for Start In this mode the current conversion is completed normally The pending conversion request will be treated immediately after the conversion is completed The conversion start t...

Page 555: ...tional control information is used to enable the request source interrupt when the requested channel conversion is completed and to enable the automatic refill process A sequential source consists of...

Page 556: ...in which to enter a conversion request is given by the write only queue input register QINR0 If there is still an empty stage V 0 in the queue the written value will be stored there bit V becomes set...

Page 557: ...trigger event EXTR 1 the signal REQTR can be taken into account with ENTR 1 or the software can write TREV 1 Both actions set the event flag EV The event flag EV 1 indicates that an external event ha...

Page 558: ...r channel numbers before lower channel numbers The parallel request source consists of a conversion request control register CRCR1 a conversion request pending register CRPR1 and a conversion request...

Page 559: ...r autoscan mode See Section 16 4 5 5 Each bit bit x x 4 7 in the conversion request control pending registers corresponds to one analog input channel The bit position directly defines the channel numb...

Page 560: ...t can be used to start conversions with a single move operation In this case the information about the channels to be converted is given as an argument in the move instruction Bit LDEV can be written...

Page 561: ...cleared data is invalid The wait for read mode for a result register can be enabled by setting bit WFR see Section 16 7 8 16 4 7 Result Generation The result generation part handles the storage of th...

Page 562: ...ction 16 7 8 for description of the result generation registers conversion result result buffer analog part 0 add sub result register 0 result register 1 result register 3 boundary values from channel...

Page 563: ...with BOUND0 then with BOUND1 Depending on the result flags lower than compare the limit checking unit can generate a channel interrupt It can become active when the valid result of the data reduction...

Page 564: ...ad value is 0 data reduction filter disabled accumulation is done over one conversion Hence a result event is generated and the valid bit VF for the result register becomes set If the reload value is...

Page 565: ...H This view delivers the 8 bit or 10 bit conversion result Accumulated read view RESRAxL H This view delivers the accumulated 9 bit or 11 bit conversion result All conversion results with or without...

Page 566: ...2 1 0 R0 7 0 0 VF DRC CHNR 6 5 4 3 2 1 0 8 bit conversion with without accumulation R9 7 R8 R7 R6 R5 R4 R3 R2 6 5 4 3 2 1 0 R1 7 R0 VF DRC CHNR 6 5 4 3 2 1 0 10 bit conversion with without accumulati...

Page 567: ...rs result interrupts Channel Interrupts Activated by the completion of any input channel conversion They are enabled according to the control bits for the limit checking The settings are defined indiv...

Page 568: ...urce event of sequential request source 0 arbitration slot 0 Event 1 Request source event of parallel request source 1 arbitration slot 1 A result event is generated according to the data reduction co...

Page 569: ...l interrupt can be triggered according to the following conditions selected by the limit check control bit field LCC LCC 000 No trigger the channel interrupt is disabled LCC 001 A channel interrupt is...

Page 570: ...888CLM Analog to Digital Converter User s Manual 16 26 V1 3 2010 02 ADC V 1 0 Figure 16 15 Channel Interrupt Routing to SR0 CHINF0 CHINF1 CHINF7 to SR1 CHINP0 CHINP1 CHINP7 channel number rh rh rh rw...

Page 571: ...This selection is done via bit SYNENx Refer to Section 16 7 9 for description of the external trigger control registers Figure 16 16 External Trigger Input The external trigger inputs to the ADC modul...

Page 572: ...reduction for result register x RCRx DRCTR Enable disable event interrupt for result register x RCRx IEN Enable disable wait for read mode for result register x RCRx WFR Enable disable valid flag res...

Page 573: ...f not already available to trigger a pending conversion request using any method described in Section 16 4 5 2 Wait for ADC conversion to be completed The source interrupt indicates that the conversio...

Page 574: ...Address List for Pages 0 3 Address Page 0 Page 1 Page 2 Page 3 CAH GLOBCTR CHCTR0 RESR0L RESRA0L CBH GLOBSTR CHCTR1 RESR0H RESRA0H CCH PRAR CHCTR2 RESR1L RESRA1L CDH LCBR CHCTR3 RESR1H RESRA1H CEH INP...

Page 575: ...Bits Type Description PAGE 2 0 rw Page Bits When written the value indicates the new page address When read the value indicates the currently active page STNR 5 4 w Storage Number This number indicat...

Page 576: ...ving The value written to the bit positions of PAGE is stored In parallel the former contents of PAGE are saved in the storage bit field STx indicated by STNR 11B Automatic restore page action The val...

Page 577: ...bal Control Register CAH Reset Value 30H 7 6 5 4 3 2 1 0 ANON DW CTC 0 rw rw rw r Field Bits Type Description CTC 5 4 w Conversion Time Control This bit field defines the divider ratio for the divider...

Page 578: ...is switched off and conversions are not possible To achieve minimal power consumption the internal analog circuitry is in its power down state and the generation of fADCI is stopped 1B The analog par...

Page 579: ...bit indicates that a conversion is currently active 0B The analog part is idle 1B A conversion is currently active SAMPLE 1 rh Sample Phase This bit indicates that an analog input signal is currently...

Page 580: ...request source 0 0B Low priority 1B High priority CSM0 1 rw Conversion Start Mode of Request Source 0 This bit defines the conversion start mode of the sequential request source 0 0B The wait for sta...

Page 581: ...ASEN0 enables arbitration slot 0 ASEN1 enables slot 1 If an arbitration slot is disabled a pending conversion request of a request source connected to this slot is not taken into account for arbitrati...

Page 582: ...5 3 rw External Trigger Selection for Request Source x This bit field defines which external trigger input signal is selected 000B The trigger input ETRx0 is selected 001B The trigger input ETRx1 is s...

Page 583: ...rol Register x CCH x 1 Reset Value 00H 7 6 5 4 3 2 1 0 0 LCC 0 RESRSEL r rw r rw Field Bits Type Description RESRSEL 1 0 rw Result Register Selection This bit field defines which result register will...

Page 584: ...rol the sample time for the input channels INPCR0 Input Class 0 Register CEH Reset Value 00H 7 6 5 4 3 2 1 0 STC rw Field Bits Type Description STC 7 0 rw Sample Time Control This bit field defines th...

Page 585: ...t source 0B The gating line is permanently 0 The source is switched off 1B The gating line is permanently 1 The source is switched on ENTR 2 rw Enable External Trigger This bit enables the external tr...

Page 586: ...w Trigger Event 0B No action 1B A trigger event is generated by software If the source waits for a trigger event a conversion request is started CEV 7 w Clear Event Bit 0B No action 1B Bit EV is clear...

Page 587: ...m value If EMPTY bit 1 there are no valid entries in the queue 00B If EMPTY bit 0 there is 1 valid entry in the queue 01B If EMPTY bit 0 there are 2 valid entries in the queue 10B If EMPTY bit 0 there...

Page 588: ...V 1 0 Rsv 7 r Reserved Returns 1 if read should be written with 0 Note This bit is initialized to 0 immediately after reset but is updated by hardware to 1 and remains as 1 shortly after 0 3 0 6 r Re...

Page 589: ...itten to the queue input register QINR0 or by an update by intermediate queue registers 0B The data is not valid 1B The data is valid RF 5 rh Refill This bit indicates if the pending request is discar...

Page 590: ...rsion request is sensitive to an external trigger event The event flag bit EV indicates if an external event has taken place and a conversion can be requested 0B Bit EV is not used to start conversion...

Page 591: ...ersion requested by Q0R0 is started V 4 rh Request Channel Number Valid This bit indicates if the data in REQCHNR RF ENSI and EXTR is valid Bit V is set if a running conversion is aborted It is reset...

Page 592: ...RF 0 REQCHNR w w w r w Field Bits Type Description REQCHNR 2 0 w Request Channel Number This bit field defines the requested channel number RF 5 w Refill This bit defines the refill functionality ENS...

Page 593: ...1 leads to a data write to the bits in CRCR1 with an automatic load event one clock cycle later CRCR1 Conversion Request Control Register 1 CAH Reset Value 00H 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 0 rwh rw...

Page 594: ...vent one clock cycle later CRPR1 Conversion Request Pending Register 1 CBH Reset Value 00H 7 6 5 4 3 2 1 0 CHP7 CHP6 CHP5 CHP4 0 rwh rwh rwh rwh r Field Bits Type Description CHPx x 4 7 x rwh Channel...

Page 595: ...ernal Trigger This bit enables the external trigger possibility If enabled the load event takes place if a rising edge is detected at the external trigger input REQTR 0B The external trigger is disabl...

Page 596: ...PR1 are reset LDEV 6 w Generate Load Event 0B No action 1B The load event is generated Rsv 7 r Reserved Returns 1 if read should be written with 0 Note This bit is initialized to 0 immediately after r...

Page 597: ...is cleared when the high byte of the register is accessed by a read command provided that bit RCRx VFCTR is set RESRxL x 0 2 Result Register x Low CAH x 2 Reset Value 00H RESR3L Result Register 3 Low...

Page 598: ...LT 1 0 7 6 rh Conversion Result This bit field contains the conversion result or the result of the data reduction filter 0 5 r Reserved Returns 0 if read should be written with 0 RESRxH x 0 2 Result R...

Page 599: ...mber of the latest register update DRC 3 rh Data Reduction Counter This bit field indicates how many conversion results have still to be accumulated to generate the final result for data reduction 0B...

Page 600: ...Result Register x View A High CBH x 2 Reset Value 00H RESRA3H Result Register 3 View A High D3H Reset Value 00H 7 6 5 4 3 2 1 0 RESULT 10 3 rh Field Bits Type Description RESULT 10 3 7 0 rh Conversio...

Page 601: ...e result control registers RCRx contain bits that control the behavior of the result registers and monitor their status VFCR Valid Flag Clear Register CEH Reset Value 00H 7 6 5 4 3 2 1 0 0 VFC3 VFC2 V...

Page 602: ...N 4 rw Interrupt Enable This bit enables the event interrupt related to the result register x An event interrupt can be generated when DRC is set to 0 after decrementing or by reload 0B The event inte...

Page 603: ...upt Flag Register CAH Reset Value 00H 7 6 5 4 3 2 1 0 CHINF7 CHINF6 CHINF5 CHINF4 CHINF3 CHINF2 CHINF1 CHINF0 rh rh rh rh rh rh rh rh Field Bits Type Description CHINFx x 0 7 x rh Interrupt Flag for C...

Page 604: ...2 1 0 CHINS7 CHINS6 CHINS5 CHINS4 CHINS3 CHINS2 CHINS1 CHINS0 w w w w w w w w Field Bits Type Description CHINSx x 0 7 x w Set Interrupt Flag for Channel x 0B No action 1B Bit CHINFR x is set and an...

Page 605: ...EVINF5 EVINF4 0 EVINF1 EVINF0 rh rh rh rh r rh rh Field Bits Type Description EVINFx x 0 1 4 7 1 0 7 4 rh Interrupt Flag for Event x This bit monitors the status of the event interrupt x 0B An event...

Page 606: ...6 EVINS5 EVINS4 0 EVINS1 EVINS0 w w w w r w w Field Bits Type Description EVINSx x 0 1 4 7 1 0 7 4 w Set Interrupt Flag for Event x 0B No action 1B Bit EVINFR x is set 0 3 2 r Reserved Returns 0 if re...

Page 607: ...0s at the end to form the final value used for comparison with the converted result For example the reset value of BOUND1 BH will translate into B0H for an 8 bit comparison and 2C0H for a 10 bit compa...

Page 608: ...the XC800 Core Add a minimum of hardware overhead Provide support for most of the operations by a Monitor Program Use standard interface to communicate with the Host a Debugger 17 1 Features The main...

Page 609: ...G1 which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application The dedicated MBC pin is used for external configuration and debugging co...

Page 610: ...tween the OCDS hardware and a specialized software called the Monitor program 17 3 1 Debug Events The OCDS system recognizes a number of different debug events which are also called breakpoints or sim...

Page 611: ...rammed values inclusively Breakpoints on Instruction Address These Instruction Pointer IP breakpoints are generated when a break address is matched for the first byte of an instruction that is going t...

Page 612: ...ddress HWBP2 or One range breakpoint on HWBP2L IRAM Read Address HWBP2H Breakpoint 3 One equal breakpoint on Instruction Address HWBP3 or One range breakpoint on HWBP3L IRAM Write Address HWBP3H Setti...

Page 613: ...functions are blocked restricted 1 No external break is possible while the core is servicing an NMI External break requested inside a NMI servicing routine will be taken only after RETI is executed 2...

Page 614: ...tion additional to the Monitor program start in such a case MBC pin is activated for up to 77 system clock SCLK cycles As the only OCDS action while temporarily suspending the core activity MBC pin is...

Page 615: ...end control bits global enable in OCDS and individual selections in SCU have values 0 after reset i e by default no module will be suspended upon a break But normally for debugging the device will be...

Page 616: ...ster 2 MMSR F2H Monitor Mode Status Register MMBPCR F3H Monitor Mode Breakpoints Control Register MMICR F4H Monitor Mode Interrupt Control Register MMDR F5H Monitor Mode Data Register HWBPSR F6H Hardw...

Page 617: ...de is still not started Monitor mode while the Monitor program is running the user code is in break Therefore an unintentional access to OCDS registers by the user software can not disturb the normal...

Page 618: ...e Description JTAGTCKS 4 rw JTAG TCK Input Select 0 JTAG TCK Input TCK_0 is selected 1 JTAG TCK Input TCK_1 is selected JTAGTDIS 5 rw JTAG TDI Input Select 0 JTAG TDI Input TDI_0 is selected 1 JTAG TD...

Page 619: ...after reset The JTAG ID for the XC886 888 devices is given in Table 17 3 JTAGTDIS1 1 rw JTAG TDI Input Select 1 0 JTAG TDI Input TDI_2 is not selected 1 JTAG TDI Input TDI_2 is selected Note If this b...

Page 620: ...ltiCAN LIN BSL is not available then the entry to the respective BSL UART or MultiCAN is decided based on their initial header frames Note UART BSL is supported only via UART module and not UART1 Note...

Page 621: ...both UART and LIN protocols will be covered in Section 18 1 2 and Section 18 1 3 respectively Table 18 2 Serial Communication Modes of the UART and LIN BSL Modes Mode Description 0 00H Transfer a user...

Page 622: ...a of the Data Block 1 1 The length of Data and EOT Blocks is defined as Block_Length in the Header Block 02H type END OF TRANSMISSION EOT EOT Block is the last block in data transmission in Mode 0 and...

Page 623: ...ta bytes NAD Node Address for Diagnostic which specifies the address of the active slave node 01H to 7EH Valid Slave Address 80H to FFH Valid Slave Address 7FH Broadcast Address For Master nodes to al...

Page 624: ...and E5H The Programming Checksum is 19H An inversion of the Programming Checksum yields the standard LIN Checksum Classic Checksum i e E6H Both Programming and LIN Checksum are supported and indicate...

Page 625: ...n When program and erase operations of Flash are restricted due to Flash Protection Mode 0 or 1 being enabled protection error code will be sent to the host This will indicate that Flash is protected...

Page 626: ...e performed once the response is sent 6 A The requested operation has been performed and is successful EOT 0 2 4 8 All others Reception of the block is successful Transmission of 4 byte data follows i...

Page 627: ...t The PC host sends test byte 80H to start the synchronization flow The timer is started on reception of the start bit 0 and stopped on reception of the last bit of the test byte 1 Then the UART BSL r...

Page 628: ...One is adopted by Mode 0 and Mode 2 while the other is adopted by the rest of the modes Data and EOT Blocks are transferred only in Mode 0 and 2 Figure 18 1 Communication Structure of the UART BSL Mod...

Page 629: ...ved program code in the XRAM Flash1 Block_Length The whole length block type data area and checksum of the following Data or EOT Blocks 2 3 1 Flash address must be aligned to the wordline address wher...

Page 630: ...ngth is provided in the previous Header Block Note No empty Data Block is allowed The EOT Block Description Last_Codelength This byte indicates the length of the program code in this EOT Block Program...

Page 631: ...T debugger Mode F 18 1 2 5 The Activation of Mode 4 Mode 4 is used to erase sector s of P Flash bank s or D Flash bank s or mass erase of all sectors in P Flash and D Flash banks The selection of the...

Page 632: ...the DFlash_Bank0_L byte selects sectors 1 and 4 of D Flash Bank 0 for erase DFlash_Bank0_H2 The sectors 8 and 9 of D Flash Bank 0 are represented are represented by bits 0 to 11 For example a value of...

Page 633: ...the user password see Chapter 3 4 1 Not used The four bytes are not used and will be ignored in Mode 6 In Mode 6 the header block is the only transfer block to be sent by the host This mode is used w...

Page 634: ...data to be sent to the host Only option 00H is available to return the chip identification number which is used to identify the particular device variant 00H Chip Identification Number MSB byte 1 LSB...

Page 635: ...Fast LIN BSL using BSL Mode protocol on single wire UART LIN Re synchronization and setup of baud rate Phase I are always performed prior to the entry of Phase II and III Thus different baud rates can...

Page 636: ...the transfer 8 bits is captured in the T2 Reload Capture register RC2H L Then the LIN BSL routine calculates the actual baud rate sets the PRE and BG values and activates the Baud Rate Generator The b...

Page 637: ...nchronize and Set up Baud rate Phase I Synchronize and Set up Baud rate Phase II Selection of Working Mode for valid command Phase III Report its status to the host SYN Break At least 13 bits low SYN...

Page 638: ...program from the host to the XRAM and Flash of the microcontroller respectively The header block has the following structure The Header Block Mode Data Description Start Addr High Low 16 bit Start Ad...

Page 639: ...N frame to acknowledge receiving correct header block to enter Fast LIN BSL where UART BSL protocol is used See Section 18 1 3 9 On successfully receipt of the Header Block the microcontroller enters...

Page 640: ...uals zero 18 1 3 4 The Activation of Modes 1 3 and 9 Mode 1 as well as Mode9 and Mode 3 are used to execute a user program in the XRAM Flash of the microcontroller at 0F000H and 0000H respectively The...

Page 641: ...ollowing structure The Header Block Mode data description can be referred at Section 18 1 2 5 18 1 3 6 The Activation of Mode 6 Mode 6 is used to enable or disable Flash protection via the given user...

Page 642: ...s Manual 18 23 V1 3 2010 02 Bootstrap Loader V1 0 The Header Block Mode data description can be referred at Section 18 1 2 6 00H Header Block Checksum 1 byte Mode Data 5 bytes 06H Mode 6 User Password...

Page 643: ...hen the host sends a Slave Response Header LIN frame A Response transfer block 9 bytes long fixed consists of four parts NAD Node Address for Diagnostic which specifies the address of the active slave...

Page 644: ...18 5 Microcontroller will stay at Fast LIN BSL and the communication structure and selection of modes will be like BSL Mode via UART as shown in Section 18 1 2 1 and Section 18 1 2 2 Figure 18 5 Fast...

Page 645: ...Save LIN message to XRAM and jump to Flash 0000H 1 Yes 3CH LIN Don t care Valid Invalid 2 2 Valid modes for LIN Checksum are Mode 8 and Mode 9 Other modes are considered invalid Save LIN message to X...

Page 646: ...t NAD is used When LSB of the user password is 1 user needs to program the NAD in the format shown in Table 18 8 Table 18 7 User Defined Parameters in relation with Unprotected Flash Address1 1 The ad...

Page 647: ...he following two cases for protected Flash 1 LSB of user password is 0 2 LSB of user password is 1 and user programmed NAD is invalid Note For a variant device with LIN BSL support it must be ensured...

Page 648: ...s a Host Command Message to the microcontroller The microcontroller will determine the current CAN network baud rate and configure the baud rate of the CAN node accordingly to enable the communication...

Page 649: ...hould send its code data sequentially in multiples of 8 code data bytes The user is limited to sending a maximum of 192 messages 18 2 2 CAN Message Object definition Host Command Message Object In the...

Page 650: ...In the Data Reception phase this message is sent by the host with a host specified Data Identifier which is defined in data bytes 6 and 7 of the Host Command message The data field contains user code...

Page 651: ...es are required to be programmed together with the actual values A check is done to verify whether the addition of the inverted value actual value and 01H will give 00H Table 18 9 User Defined Paramet...

Page 652: ...8 User mode 7 8 Boot ROM 3 1 Boot ROM operating mode 3 41 BootStrap Loader Mode 3 42 OCDS mode 3 43 User JTAG mode 3 43 User mode 3 42 Booting scheme 7 8 Bootstrap loader 3 42 4 9 4 14 18 1 Fast LIN B...

Page 653: ...4 32 Central Processing Unit 2 1 Chip identification number 1 17 Circular stack memory 4 5 Clock management 7 15 Clock source 7 13 Clock system 7 11 Register description 7 17 Conversion error 16 4 Con...

Page 654: ...3 5 External oscillator 7 11 7 13 F Fast LIN BSL 18 25 Flash 4 1 Endurance 4 5 Erase mode 4 11 Non volatile 4 1 Operating modes 4 11 Power down mode 4 11 Program mode 4 11 Ready to read mode 4 11 Sec...

Page 655: ...sion 3 13 Save and restore 3 14 Memory protection 3 6 Minimum erase width 4 4 Minimum program width 4 9 Modulation 14 15 Monitor mode control 17 2 Monitor RAM 17 2 Data 17 7 Stack 17 7 Monitor ROM 17...

Page 656: ...r description 2 3 Program control 2 1 Program counter 2 3 Program Flash 4 2 4 3 Parallel Read 4 5 Program memory 3 4 Program status word 2 4 Pull down device 6 8 Pull up device 6 8 Pulse width modulat...

Page 657: ...2 Port control 13 20 Register description 13 24 Register map 13 23 Timer operations 13 14 Timer T12 14 3 Capture mode 14 9 Center aligned mode 14 4 Compare mode 14 6 Dead time 14 8 Duty cycle 14 8 Edg...

Page 658: ...ser s Manual 19 7 V1 3 2010 02 Window boundary 9 2 Wordline address 4 6 Write buffers 4 9 Write result phase 16 5 X XC886 888 Device configuration 1 2 Device profile 1 3 Feature summary 1 4 Functional...

Page 659: ...2 CAN_NIPRx 15 66 CAN_NPCRx 15 68 CAN_NSRx 15 63 CAN_PANCTR 15 48 CC63RH 14 53 CC63RL 14 53 CC63SRH 14 54 CC63SRL 14 54 CC6xRH 14 48 CC6xRL 14 48 CC6xSRH 14 49 CC6xSRL 14 48 CCU6_PAGE 14 33 CD_CON 11...

Page 660: ...4 5 28 ISH 14 80 ISL 14 79 ISRH 14 86 ISRL 14 85 ISSH 14 84 ISSL 14 83 L LCBR 16 63 M MCMCTR 14 78 MCMOUTH 14 77 MCMOUTL 14 75 MCMOUTSH 14 74 MCMOUTSL 14 73 MD4 10 9 MDUCON 10 11 MDUSTAT 10 13 MDx x 0...

Page 661: ...2 45 PISEL0H 14 38 PISEL0L 14 37 PISEL2 14 39 PLL_CON 7 18 PMCON0 7 9 8 5 9 8 PMCON1 8 7 10 5 11 14 12 44 13 21 14 26 15 44 16 7 PMCON2 8 8 12 24 13 21 PORT_PAGE 6 11 PRAR 16 36 PSLR 14 72 PSW 2 4 Px_...

Page 662: ...T2L 13 28 T2MOD 13 24 TBL 12 51 TCON 5 24 5 29 13 11 TCTR2H 14 64 TCTR2L 14 62 TCTR4H 14 66 TCTR4L 14 65 TCTROH 14 60 TCTROL 14 59 THx x 0 1 13 10 TLx x 0 1 13 10 TMOD 13 12 TRPCTRH 14 71 TRPCTRL 14 6...

Page 663: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG...

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