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C O M M A N D R E F E R E N C E
Command Reference
116
LDC-3700C Series
C H A P T E R
4
The TEC:ENABle:COND command sets the status condition enable register of the TEC
operations. These conditions are summarized in bit 1 of the status byte.
Parameters
An <nrf value> whose sum represents the enabled bits:
Notes
The enabled TEC conditions can be read by using the TEC:ENABle:COND? query.
The TEC condition status can be monitored by the TEC:COND? query. If any of the
enabled TEC conditions are true, bit 1 of the status byte register will be set.
The enable registers normally retain their values at power-up (as they were at power-
down) unless the power-on status clear flag is set true (see *PSC, Chapter 3).
Examples
"TEC:ENAB:COND 513" -action: enables the TEC status condition register so that the
Output Out of Tolerance and TE Current Limit conditions will be reported in the status
byte register.
"Tec:Enable:Cond #H0DFB" -action: enables the TEC status condition register so that
any and all of the above conditions will be reported in the status byte register.
TEC:ENABle:COND
C
OMMON
D
EVICE
D
EPENDENT
F
RONT
P
ANEL
1 - TE Current Limit
256 - N/A
2 - Voltage Limit Error
512 - Output Out of Tolerance
4 - N/A
1024 - Output On
8 - High Temperature Limit
2048 - Ready for Calibration Data
16 - TEC Interlock Enable
4096 - N/A
32 - Booster Enable
8192 - N/A
64 - Sensor Open
16384 - N/A
128 - TE Module Open
32768 - N/A
Summary of Contents for LDC-3700C Series
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Page 8: ...L I S T O F FIG U R E S vi LDC 3700C Series...
Page 10: ...L I S T O F TA B L E S viii LDC 3700C Series...
Page 78: ...RE M O T E O PE R A T I ON Command Syntax 62 LDC 3700C Series C H A P T E R 3...
Page 150: ...C O M M A N D RE F E R E N C E Command Reference 134 LDC 3700C Series C H A P T E R 4...