IDT 5P49V6965, Register Descriptions And Programming Manual

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17 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
NOTE: Bit D6 is not used for 5P49V6967 and 5P49V6968 as these products have only a crystal input
D2 0 en_refmode
Enable path from reference clock to OUT1. Set to 1 when OUT1 is a copy of the
reference clock (= OUT0). Set to 0 when using FOD1 for OUT1.
D1 0 SP
SD/OE input pin is active low if this bit is 0 and active high if this bit is 1. (If D0 = 0 then
D1 reverses SD/OE pin polarity, affecting OE bits in output polarity. If D0 = 1, SD/OE
pin = 1 causes global shutdown).
D0 0
en_global
shutdown
D1 reverses SD/OE pin polarity, affecting OE bits in output buffers and SD/OE input pin
is shutdown (SD) if this bit is 1.
Table 26. RAM6 – 0x68: CLK_OE/Shutdown Function
Bits Default Value Name Function
D7 1 CLK0_OE See Table 24 – This is bit OEn for output 0.
D6 1 CLK1_OE See Table 24 – This is bit OEn for output 1.
D5 1 CLK2_OE See Table 24 – This is bit OEn for output 2.
D4 1 CLK3_OE See Table 24 – This is bit OEn for output 3.
D3 1 CLK4_OE See Table 24 – This is bit OEn for output 4.
D2 1 clk0_slewrate[1]
CLK0 slew rate setting bit[1]
11 = Fastest
00 = Slowest (20% slower than 11)
D1 1
clk0_pwr_sel[1:0]
Clock output driver power supply voltage is indicated by these bits.
D1 D0 = 0x indicates 1.8V
D1 D0 = 10 indicates 2.5V
D1 D0 = 11 indicates 3.3V
D0 1
Table 27. RAM6 – 0x69: CLK_OS/Shutdown Function
Bits Default Value Name Function
D7 1 CLK0_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D6 1 CLK1_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D5 1 CLK2_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D4 1 CLK3_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D3 1 CLK4_OS CLK_OS checks the shut down truth table. See Shutdown Function section.
D2 1 clk0_slewrate[0]
Depends on slew rate (depends on Shutdown function/truth table) – Set slew rate for
clk0.
D1 0
otp_pwr_sel[1:0]
Set Output Amplitude for OTP voltage:
Factory reserved
Use D1 D0 = 00.
D0 0
Table 25. RAM1 – 0x10: Primary Source and Shutdown Register (Cont.)
Bits Default Value Name Function