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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
VersaClock 6E products 5P49V6967 and 5P49V6968 have LVCMOS outputs on output 3. Therefore, bits D7, D6 and D5 in registers 0x64
should be set to 001 and D4 and D3 set to 00 to implement the same.
Table 112. RAM6 – 0x64: Clock3 Output
Bits
Default Value
Name
Function
D7
0
CLK3_cfg[2]
These bits give us the output type configuration mode.
For D7, D6, D5 respectively:
(D7, D6, D5) = 000: low-voltage positive/pseudo emitter-coupled logic (LVPECL);
(D7, D6, D5) = 001: CMOS;
((D7, D6, D5) = 010: HCSL33;
(D7, D6, D5) = 011: Low Voltage Differential Signal (LVDS);
(D7, D6, D5) = 100: CMOS2;
(D7, D6, D5) = 101: CMOSD;
(D7, D6, D5) = 110: HCSL25.
D6
1
CLK3_cfg[1]
D5
1
CLK3_cfg[0]
D4
1
clk3_pwr_sel[1:0]
Output Drive Voltage is set by those bits.
D4 D3 = 00 sets 1.8V.
D4 D3 = 10 sets 2.5V.
D4 D3 = 11 sets 3.3V.
D3
1
D2
0
unused bit
Unused Factory reserved bit.
D1
1
CLK3_slew[1]
Slew rate control for CMOS single-ended.
D1 D0 = 00 then output slew rate is 0.8*Normal.
D1 D0 = 01 then output slew rate indicates 0.85*Normal.
D1 D0 = 10 then output slew rate indicates 0.9*Normal.
D1 D0 = 11 then output slew rate indicates 1*Normal.
D0
1
CLK3_slew[0]
Table 113. RAM6 – 0x65: Clock3 Output Configuration
Bits
Default Value
Name
Function
D7
0
CLK3_slew_diff[5:0]
Unused register bits.
D6
0
D5
0
D4
0
D3
0
D2
0
SDOE_CLK3
SDOE_CLK3 = 1 causes OUT3 to disable to Hi-Z when disabled with SD/OE pin.
SDOE_CLK3 = 0 causes OUT3 to disable to High/Low when disabled with SD/OE pin.
D1
0
clk3_amuxen2
This bit is used to disable the output value.
Active High (1) to disable output.
D0
0
en_clkbuf3
This bit is used to enable the clock output.
Active High (1) to enable the clock output.
