IDT 5P49V6965 Register Descriptions And Programming Manual Download

Page: 8 / 58

August 30, 2018

VersaClock

6E Family Register Descriptions and Programming Guide

Table 9. RAM0 – 0x02: Factory Reserved Bits - ADC Gain Setting

Bits

Default Value

Name

Function

ADC gain[7:0]

ADC gain setting - Factory reserved bits

Table 10. RAM0 – 0x03: Factory Reserved Bits - ADC Gain Setting

Bits

Default Value

Name

Function

ADC gain[15:8]

ADC gain setting - Factory reserved bits

Table 11. RAM0 – 0x04: Factory Reserved Bits - ADC OFFSET

Bits

Default Value

Name

Function

ADC offset[7:0]

ADC offset - Factory reserved bits

Summary of Contents for 5P49V6965

Page 1: ...s all the information to set up the device s output frequencies When these configuration tables are programmed the device will automatically load the RAM registers with the desired configuration on po...

Page 2: ...and Functionality Description 15 Shutdown Function 15 Setting Up a Low Power Shutdown Mode through I2C 16 Crystal Load Capacitor Registers 18 Short Example of Programming Crystal 18 PLL Pre Divider Op...

Page 3: ...alues into the RAM registers that shadow the target OTP registers Table 4 and initiating the internal programming sequence for the desired register range Users should not write to the Trim RAM in addr...

Page 4: ...is now complete and the part will operate per the configuration settings 3 If OTP_ burned bit D7 1 in the OTP Control register Table 7 this indicates that the four OTP user configuration tables are un...

Page 5: ...ite registers 0x73 to 0x78 following the procedure in Table 5 Set burn register source address range and destination register bank CFG0 1 2 or 3 4 Write register 0x72 0xF0 Reset burn bit 5 Write regis...

Page 6: ...0x72 set to F8 4 Wait 500ms 5 Reset Burn Start Bit 0x72 set to F0 In System VersaClock 6E OTP Non Volatile Programming via I2 C For in system programming of OTP it is required to power the VDDA and V...

Page 7: ...P content Table 7 RAM0 0x00 OTP Control Register Bits Default Value Name Function D7 1 OTP_burned It s an active low state that indicates all the OTP burn process is done D7 1 tells the chip that OTP...

Page 8: ...DC gain setting Factory reserved bits D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 10 RAM0 0x03 Factory Reserved Bits ADC Gain Setting Bits Default Value Name Function D7 0 ADC gain 15 8 ADC gain setting...

Page 9: ...ction D7 0 ADC offset 15 8 ADC offset Factory reserved bits D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 13 RAM0 0x06 Factory Reserved Bits Bits Default Value Name Function D7 0 TEMPY 7 0 Factory reserved...

Page 10: ...erved bits D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1 Table 16 RAM0 0x09 Factory Reserved Bits Bits Default Value Name Function D7 1 test 3 0 Factory reserved bits D6 1 D5 1 D4 1 D3 1 NP 3 0 Factory reserved...

Page 11: ...D7 0 bandgap_trim_dn 5 0 bandgap voltage trim one step is 1 2mV lower than current D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 unused bit D0 0 unused bit Table 20 RAM0 0x0D Factory Reserved Bits Bits Default Value...

Page 12: ..._R_trim trim for R variation 1LSB is 10 default is in the middle level D3 0 D2 1 D1 0 CLK4_amp 0 clk_amp tune the amplitude of PAD 1LSB is 10 default is in the middle level D0 0 CLK3_amp 0 clk_amp tun...

Page 13: ...s 0x25 0x025 0x07F 0x0D9 0x133 Output Divider1 Fractional Settings 0x26 0x026 0x080 0x0DA 0x134 Output Divider 1 Step Spread Configuration Register 0x27 0x027 0x081 0x0DB 0x135 Output Divider 1 Step S...

Page 14: ...ngs 0x46 0x046 0x0A0 0x0FA 0x154 Output Divider 3 Step Spread Configuration Register 0x47 0x047 0x0A1 0x0FB 0x155 Output Divider 3 Step Spread Configuration Register 0x48 0x048 0x0A2 0x0FC 0x156 Outpu...

Page 15: ...p Spread Configuration Register 0x59 0x059 0x0B3 0x10D 0x167 Output Divider 4 Spread Modulation Rate Configuration Register 0x5A 0x05A 0x0B4 0x10E 0x168 Output Divider 4 Spread Modulation Rate Configu...

Page 16: ...single ended CMOS by writing 0x00 to registers 0x68 3 Enable shutdown functionality by either writing 0x83 or 0x43 to register 0x10 for crystal clock source or external clock respectively 4 Disable a...

Page 17: ...ut 2 D4 1 CLK3_OE See Table 24 This is bit OEn for output 3 D3 1 CLK4_OE See Table 24 This is bit OEn for output 4 D2 1 clk0_slewrate 1 CLK0 slew rate setting bit 1 11 Fastest 00 Slowest 20 slower tha...

Page 18: ...programmability All these capacitors combined make the load capacitance for the crystal Capacitance on pin X1 Cx1 Ci1 Cs1 Ce1 Capacitance on pin X2 Cx2 Ci2 Cs2 Ce2 Total Crystal Load Capacitance CL C...

Page 19: ...s_prediv bits see Figure 3 Table 31 and Table 32 explains the bit selections Table 29 RAM1 0x13 Factory Reserved Bits Bits Default Value Name Function D7 0 xtal_load_cap_x2 5 0 Add 6 92pF load capacit...

Page 20: ...t D7 for divide by 2 Use Bypass_prediv bit in Table 32 for divide by 1 When Bypass_prediv is 1 register 0x15 setting is don t care When Sel_prediv2 is 1 Ref_div 6 0 setting is don t care D5 0 D4 0 D3...

Page 21: ...5 100 FB_intdiv 11 0 DEC2HEX 100 0 64 or 0000 0110 0100 binary Table 33 RAM1 0x11 VCO Band and Factory Reserved Bits Bits Default Value Name Function D7 1 unused Unused Factory reserved bit D6 1 unuse...

Page 22: ...D2 01 selects 1st order D3 D2 10 selects 2nd order D3 D2 11 selects 3rd order D2 0 sdm_order_cfg 0 D1 0 i2c_ssce Factory reserved bit D0 0 unused Unused Factory reserved bit Table 36 RAM1 0x19 Feedba...

Page 23: ...2 0 D1 0 D0 0 Table 39 RAM1 0x1C Factory Reserved Bits Bits Default Value Name Function D7 1 calibration_start Forces VCO band calibration manually Needs to be toggled from 0 to 1 to activate the VCO...

Page 24: ...from 0 to 450uA D6 1 D5 1 D4 0 D3 1 en_vco Enable or disable the VCO block VCO needs to be enabled by default D2 1 i2c_bypb_dl Bypass global reset 0 means the reset is bypassed 1 means the part will r...

Page 25: ...ogrammable Cz 500pF C2 is the 2nd Pole capacitor and programmable with Register 0x1E R3 and C3 are the 3rd pole RC values programmable with register x1F The Icp charge pump current is programmable in...

Page 26: ...04 ROUND2INT 4194304 4194304 ODx_frcdiv 23 0 DEC2HEX 4194304 40 00 00 Spread spectrum capability is contained within the Fractional N output dividers associated with each output clock When applied tri...

Page 27: ...early from the non spread value of N followed by a linear ramp back down to the non spread value of N N is always greater than or equal to the non spread value of N therefore the output frequency is a...

Page 28: ...less number of FOUT periods that fit in a half period of FSS Calculate the step size Since the spread spectrum ramp as implemented only decreases the frequency of FOUT then the actual offset for down...

Page 29: ...Eq 9 ODx_offset dec 0 19191919 0 5 100 14 19191919 2 0 15643939 From Eq 10 224 0 15643939 2624617 502 Odx_offset 29 0 280C69 Some calculated examples with SSCE 0 for frequency margining purposes Tabl...

Page 30: ...d in integer mode The following pages explain how to set up the MUX Table 46 FOD1 Register Table Register Offsets Output MHz 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2C 0x2E 0x2F 97 14...

Page 31: ...norm1 0000 FOD1 and OUT1 are not used 00x1 FOD1 uses clock from PLL and OUT1 uses clock from FOD1 1100 FOD1 disabled and OUT1 uses clock from OUT0 En_refmode needs to be 1 1111 FOD1 uses clock from OU...

Page 32: ...T3 uses clock from FOD3 En_aux2 needs to be 1 int_mode3 sets integer mode for FOD3 fractional settings will be ignored D2 0 sel_ext3 D1 0 int_mode3 D0 1 en_fod3 Table 50 RAM5 0x51 Output Divider 4 Con...

Page 33: ...12 bit spread over 2 registers x2D and x2E D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 52 RAM2 0x2E Output Divider 1 Integer Part Bits Default Value Name Function D7 1 OD1_intdiv 3 0 Output divider 1 int...

Page 34: ...ved bit D0 0 unused bits Unused Factory reserved bit Table 55 RAM4 0x4D Output Divider 3 Integer Part Bits Default Value Name Function D7 0 OD3_intdiv 11 4 Output divider 3 integer part has 12 bit spr...

Page 35: ...lock frequency 24 bits spread on 3 registers If ODx_ssce 0 contents of ODx_period and ODx_step are don t care only the ODx_offset are taken into account If ODx_ssce 1 means the spread is enabled for c...

Page 36: ...and x25 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 60 RAM2 0x23 Output Divider 1 Fractional Settings Bits Default Value Name Function D7 0 OD1_offset 21 14 30 bits to configure the fraction value of FO...

Page 37: ...ssce Enable spread spectrum with center spread offset Active High D0 0 Unused Unused Factory reserved bit Table 63 RAM2 0x26 Output Divider 1 Step Spread Configuration Register Bits Default Value Name...

Page 38: ...r 1 Spread Modulation Rate Configuration Register Bits Default Value Name Function D7 0 OD1_period 12 5 13 bits used to configure spread modulation period in register x29 and x2A D6 0 D5 0 D4 0 D3 0 D...

Page 39: ...and x35 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 69 RAM3 0x33 Output Divider 2 Fractional Settings Bits Default Value Name Function D7 0 OD2_offset 29 6 30 bits to configure the fraction value of FOD...

Page 40: ...ce Enable spread spectrum with center spread offset Active High D0 0 unused Bit Unused Factory reserved bit Table 72 RAM3 0x36 Output Divider 2 Step Spread Configuration Register Bits Default Value Na...

Page 41: ...ider 2 Spread Modulation Rate Configuring Register Bits Default Value Name Function D7 0 OD2_period 12 5 13 bits used to configure spread modulation period in register x39 and x3A D6 0 D5 0 D4 0 D3 0...

Page 42: ...and x45 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 78 RAM4 0x43 Output Divider 3 Fractional Settings Bits Default Value Name Function D7 0 OD3_offset 29 6 30 bits to configure the fraction value of FOD...

Page 43: ...ssce Enable spread spectrum with center spread offset Active High D0 0 unused Unused Factory reserved bit Table 81 RAM4 0x46 Output Divider 3 Step Spread Configuration Register Bits Default Value Name...

Page 44: ...ut Divider 3 Spread Modulation Rate Configuring Register Bits Default Value Name Function D7 0 OD3_period 12 5 13 bits used to configure spread modulation period in register x49 and x4A D6 0 D5 0 D4 0...

Page 45: ...and x55 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Table 87 RAM5 0x53 Output Divider 4 Fractional Settings Bits Default Value Name Function D7 0 OD4_offset 29 6 30 bits to configure the fraction value of FOD4...

Page 46: ...e Enable spread spectrum with center spread offset Active High D0 0 Unused bits Unused Factory reserved bit Table 90 RAM5 0x56 Output Divider 4 Step Spread Configuration Register Bits Default Value Na...

Page 47: ...der 4 Spread Modulation Rate Configuring Register Bits Default Value Name Function D7 0 OD4_period 12 5 13 bits used to configure spread modulation period in register x59 and x5A D6 0 D5 0 D4 0 D3 0 D...

Page 48: ...its for a fraction The unit used for the skew is degrees of delay of the edge The VCO frequency is first divided by 2 before it goes to the Output Divider The number programmed for skew is the amount...

Page 49: ...follows Addr Byte 0x2B 00 OD1_intskew 11 4 00 most likely it is already 00 if so skip this line 0x2C 10 OD1_intskew 3 0 1 0x2F 74 OD1_frskew 5 0 74 0x76 C3 Set I2C_Global_Reset 0x76 E3 Release I2C_Glo...

Page 50: ...reserved bit D1 0 unused bits Unused Factory reserved bit D0 0 en_aux Factory reserved bit Table 97 RAM2 0x2F Output Divider 1 Skew Fractional Part Bits Default Value Name Function D7 0 unused bits Un...

Page 51: ...d bit D1 0 unused bits Unused Factory reserved bit D0 0 en_aux Factory reserved bit Table 100 RAM3 0x3F Output Divider 2 Skew Fractional Part Bits Default Value Name Function D7 0 unused bits Unused F...

Page 52: ...Unused Factory reserved bit D1 0 unused bits Unused Factory reserved bit D0 0 en_aux Factory reserved bit Table 103 RAM4 0x4F Output Divider 3 Skew Fractional Part Bits Default Value Name Function D7...

Page 53: ...its Default Value Name Function D7 0 OD4_intskew 3 0 12 bits are used to set Output Divider4 skew integer part in register x5B and x5C D6 0 D5 0 D4 0 D3 0 unused bits Unused Factory reserved bit D2 0...

Page 54: ...0 HCSL33 D7 D6 D5 011 Low Voltage Differential Signal LVDS D7 D6 D5 100 CMOS2 D7 D6 D5 101 CMOSD D7 D6 D5 110 HCSL25 D6 0 CLK1_cfg 1 D5 1 CLK1_cfg 0 D4 1 clk1_pwr_sel 1 0 Output Drive Voltage is set b...

Page 55: ...11 sets 3 3V D3 1 D2 0 unused bit Unused Factory reserved bit D1 1 CLK2_slew 1 Slew rate control for CMOS single ended D1 D0 00 then output slew rate is 0 8 Normal D1 D0 01 then output slew rate indic...

Page 56: ...r_sel 1 0 Output Drive Voltage is set by those bits D4 D3 00 sets 1 8V D4 D3 10 sets 2 5V D4 D3 11 sets 3 3V D3 1 D2 0 unused bit Unused Factory reserved bit D1 1 CLK3_slew 1 Slew rate control for CMO...

Page 57: ...11 sets 3 3V D3 1 D2 0 Unused Bit Unused Factory reserved bit D1 1 CLK4_slew 1 Slew rate control for CMOS single ended D1 D0 00 then output slew rate is 0 8 Normal D1 D0 01 then output slew rate indic...

Page 58: ...and other countries Other trademarks used herein are the property of IDT or their respective third party owners For datasheet type definitions and a glossary of common terms visit www idt com go gloss...

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