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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Table 35. RAM1 – 0x18: Feedback Integer Divider Bits
Bits
Default Value
Name
Function
D7
0
FB_intdiv[3:0]
The Feedback Integer Divider Register has 12 bits spread on 2 registers 0x17 and 0x18.
D6
0
D5
0
D4
0
D3
0
sdm_order_cfg[1]
Factory Reserved bits. These both bits are for Sigma Delta Modulator setting.
D3 D2 = 00: sdm bypass,
D3 D2 = 01: selects 1st order,
D3 D2 = 10: selects 2nd order,
D3 D2 = 11: selects 3rd order.
D2
0
sdm_order_cfg[0]
D1
0
i2c_ssce
Factory reserved bit.
D0
0
unused
Unused Factory reserved bit.
Table 36. RAM1 – 0x19: Feedback Fractional Divider Registers
Bits
Default Value
Name
Function
D7
0
FB_frcdiv[23:16]
The Feedback fractional divider has 24 bits divided amongst 3 registers (0x19, 0x1A and
0x1B).
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Table 37. RAM1 – 0x1A: Feedback Fractional Divider Bits
Bits
Default Value
Name
Function
D7
0
FB_frcdiv[15:8]
The Feedback fractional divider has 24 bits divided amongst 3 registers (0x19, 0x1A
and 0x1B).
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
