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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Table 62. RAM2 – 0x25: Output Divider 1 Fractional Settings
Bits
Default Value
Name
Function
D7
0
OD1_offset[5:0]
30 bits to configure the fraction value of FOD1 in register address x22, x23, x24 and x25.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
OD1_ssce
Enable spread spectrum with center spread offset. Active High.
D0
0
Unused
Unused Factory reserved bit.
Table 63. RAM2 – 0x26: Output Divider 1 Step Spread Configuration Register
Bits
Default Value
Name
Function
D7
0
OD1_step[7:0]
24 bits used for modulation step size in register x26 x27 and x28.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Table 64. RAM2 – 0x27: Output Divider 1 Step Spread Configuration Register
Bits
Default Value
Name
Function
D7
0
OD1_step[15:8]
24 bits used for modulation step size in register x26 x27 and x28.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
