41
©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Table 74. RAM3 – 0x38: Output Divider 2 Step Spread Configuration Register
Bits
Default Value
Name
Function
D7
0
OD2_step[23:16]
24 bits used for modulation step size in register x36 x37 and x38.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Table 75. RAM3 – 0x39: Output Divider 2 Spread Modulation Rate Configuring Register
Bits
Default Value
Name
Function
D7
0
OD2_period[12:5]
13 bits used to configure spread modulation period in register x39 and x3A.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Table 76. RAM3 – 0x3A: Output Divider 2 Spread Modulation Rate Configuring Register
Bits
Default Value
Name
Function
D7
0
OD2_period[4:0]
13 bits used to configure spread modulation period in register x39 and x3A.
D6
0
D5
0
D4
0
D3
0
D2
0
unused bit
Unused Factory reserved bit.
D1
0
unused bit
Unused Factory reserved bit.
D0
0
unused bit
Unused Factory reserved bit.