IDT 5P49V6965, Register Descriptions And Programming Manual

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4 ©2018 Integrated Device Technology, Inc. August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
VersaClock 6E Family Power-Up Behavior
On power-up, the following RAM register loading sequence occurs:
1. The RAM registers always initialize to a hard-wired set of default values, which are also the 'Default register values' for OTP shown in
subsequent tables.
2. If OTP_ burned bit D7 = 0 in the OTP Control register ( Table 7 ), this indicates that the both the Trim OTP tables and at least one of
the four OTP user configuration tables have been programmed.
• Factory programmed product is typically shipped in this condition. Device has factory trim performed and with required
customization written into OTP memory. IDT programs user customization at factory test. Please visit our website for device
customization request.
• Trim RAM data will be updated from the Trim OTP registers into the appropriate trim RAM registers, overwriting the initial default
values.
• Configuration data will be read from the one of the four OTP user configuration tables into the appropriate configuration RAM
registers, overwriting the initial default values. When powered up in I
2
C mode, the first configuration table, CFG0, is loaded. When
powered up in selection-pin mode, the SEL0 and SEL1 input pins are decoded to select one of the four configuration tables ( Table
23 ).
• Initialization is now complete, and the part will operate per the configuration settings.
3. If OTP_ burned bit D7 = 1 in the OTP Control register ( Table 7 ), this indicates that the four OTP user configuration tables are
unconfigured.
• Un-programmed product is shipped in this condition and ready for user self-program and customization.
• Configuration RAM data remains at the hard-wired set of default values.
• Initialization is now complete, and the part will operate per the default configuration settings.
• When powered up in I
2
C mode, the Configuration RAM registers can be written with the user's desired settings by the host system,
and the clock generator operated without ever programming any of the four OTP user configuration tables. Alternatively, the host
system (or a programming system) can program one of more of the four OTP user configuration tables, and also clear the OTP_
burned bit D7 in the OTP Control register (
Table 7 ) to 0. The VersaClock 6E device will follow the behavior according to section 0
above for subsequent power ups.
Table 4. RAM Register Map Summary
Register Range RAM Register Block
Corresponding OTP Register
Block Name
Corresponding OTP Register Block Address
Range
0x00 OTP Control OTP Control 0x000
0x01–0x0F Trim Trim 0x000–0x00F
0x10–0x1F Configuration–Main
CFG0
CFG1
CFG2
CFG3 0x010–0x069
0x06A–0x0C3
0x0C4–0x11D
0x11E–0x177
0x20–0x2F Configuration–CLK1
0x30–0x3F Configuration–CLK2
0x40–0x4F Configuration–CLK3
0x50–0x5F Configuration–CLK4
0x60–0x69 Configuration–Outputs
0x6A–0x6F Factory Use — —
0x70–0x7F OTP Control — —
0x80–0x8F Unused RAM — —
0x90–0x9F Factory Use — —