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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
Table 71. RAM3 – 0x35: Output Divider 2 Fractional Settings
Bits
Default Value
Name
Function
D7
0
OD2_offset[5:0]
30 bits to configure the fraction value of FOD2 in register address x32, x33, x34 and x35.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
OD2_ssce
Enable spread spectrum with center spread offset. Active High.
D0
0
unused Bit
Unused Factory reserved bit.
Table 72. RAM3 – 0x36: Output Divider 2 Step Spread Configuration Register
Bits
Default Value
Name
Function
D7
0
OD2_step[7:0]
24 bits used for modulation step size in register x36 x37 and x38.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Table 73. RAM3 – 0x37: Output Divider 2 Step Spread Configuration Register
Bits
Default Value
Name
Function
D7
0
OD2_step[15:8]
24 bits used for modulation step size in register x36 x37 and x38.
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
