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©2018 Integrated Device Technology, Inc.
August 30, 2018
VersaClock
®
6E Family Register Descriptions and Programming Guide
SH bit = “Shutdown Bit”: Enable shutdown mode where the SD/OE pin can disable more than just outputs.
SP bit = “SD/OE pin Polarity Bit”: Set the polarity of the SD/OE pin where outputs enable or disable. Only works with OE, not with SD.
OSn bit = “Output Suspend Bit”: Permanently disable an output, independent of SD/OE pin.
OEn bit = “Output Enable Bit”: Permanently enable an output, independent of SD/OE pin. Only works with OE, not with SD.
SDOE bit = “Output Disabled State”: Set the output state to either driven High/Low or Hi-Z when disabled with the SD/OE pin.
SD/OE pin = Physical pin on the device.
SH and SP bits exist only once and affect all outputs. Other bits exist per output and affect that specific output.
Setting Up a Low-Power Shutdown Mode through I
2
C
1. Tristate the outputs by writing b'001ss000' to registers 0x60, 0x62, 0x64, and 0x66 where ss = 00, 10, or 11 for output clock supply
voltages 1.8V, 2.5V, or 3.3V.
2. Program all outputs to single-ended CMOS by writing 0x00 to registers 0x68.
3. Enable shutdown functionality by either writing 0x83 or 0x43 to register 0x10, for crystal clock source or external clock respectively.
4. Disable all output dividers by writing 0x80 to registers 0x21, 0x31, 0x41, and 0x51.
5. Take the SD/OE input pin 7 high.
Table 24. Shutdown Truth Table
SH bit
SP bit
OSn bit
OEn bit
SD/OE bit
SD/OE pin
OUTn
0
x
1
0
x
x
Output Active
x
0
1
1
x
0
Output Active
0
1
1
1
x
1
Output Active
1
x
1
0
x
0
Output Active
0
0
1
1
0
1
Output Driven Logic “1” (High/Low)
x
1
1
1
0
0
Output Driven Logic “1” (High/Low)
1
x
x
x
0
1
Global Shutdown, Output Driven Logic “1” (High/Low)
x
x
0
x
x
x
Output Tri-stated (Hi-Z)
0
0
1
1
1
1
Output Tri-stated (Hi-Z)
x
1
1
1
1
0
Output Tri-stated (Hi-Z)
Table 25. RAM1 – 0x10: Primary Source and Shutdown Register
Bits
Default Value
Name
Function
D7
1
en_xtal
Crystal Oscillator circuit is disabled with 0 and enabled with 1.
D6
0
en_clkin
CLKIN differential input circuit is disabled with 0 and enabled with 1.
D5
1
unused
Unused Factory reserved bit.
D4
0
unused
Unused Factory reserved bit.
D3
0
en_ref_doubler
Use “en_ref_doubler” is 1 to double the reference frequency for the Phase Frequency
Detector.
Use “en_ref_doubler” is 0 to bypass the doubler.
