
1022410 – 0001 Rev. 2
UMOD hardware theory of operation 3–25
Figure 3-11
Control processor block diagram
NMI
CP
SUPERVISOR
RESET
MICRO-
PROCESSOR
128 K TES
BOOT PROM
64 K UMOD
BOOT PROM
256 K FLASH
MEMORY
256 K FLASH
MEMORY
REAL-TIME
CLOCK
FRAMING
UNIT MODULE
BER TEST
LOGIC
TIMING
GENERATOR
INTERFACE
ADDRESS/DATA/CONTROL BUS
ADDRESS/DATA/CONTROL BUS
448 K
PSRAM
8 K
EEPROM
MODULATOR/
DEMODULATOR
INTERFACE
ADDRESS/DATA/CONTROL BUS
TERRESTRIAL
INTERFACE
MODULE
CHANNEL
CODING
INTERFACE
SERIAL
COMMUNICATIONS
CONTROLLER
(SCC)
ADDRESS/DATA/CONTROL BUS
QUAD
UART
SCC INTERRUPT
DIAGNOSTIC PORT
SATELLITE PORT
QUART INTERRUPT
TERMINAL/KEYBOARD/
DISPLAY PORT
ASYNC DATA PORT
MULTIDROP PORT 2
MULTIDROP PORT 1
The timing generator (TGEN) provides all clock signals used on
the UMOD module other than processor and baud rate clocks. The
timing generator consists of a transmit timing generator (TXTG)
and a receive timing generator (RXTG).
Timing generator
description