
1022410 – 0001 Rev. 2
3–8 UMOD hardware theory of operation
88
The channel encoding section of the UMOD motherboard
formats the data before it is modulated.
The encoding circuitry (see figure 3-2 on page 3–8) performs the
functions specified in IESS-308 (IDR) and IESS-309 (IBS) that
relate to forward error correction and scrambling. [In addition, this
circuit performs the channel coding functions required to operate
in a closed HNS Telephony Earth Station (TES) network as well
as the HNS Personal Earth Station (PES) network.]
Figure 3-2
Channel encoding circuit block diagram
The channel encoding circuit performs the following functions:
•
Scrambling data for energy dispersion purposes
•
[Inserting the Overhead Channel Frame Marker and Data
Packet]
•
Differential encoding for resolution of phase ambiguity in
the demodulator during initial acquisition and following
cycle slips
•
Converting FEC Rate 1/2 to Rate 3/4 or Rate 7/8
(Puncturing)
•
FEC convolutional encoding
•
Reed-Solomon encoding (IESS-308 Rev. 6A)
•
4-level interleaver per IESS-308.
•
Concatenated Viterbi/Reed-Solomon encoding
The encoding circuit operates in the following modes:
•
BPSK—Rate 1 (no FEC); Rates 1/2, 3/4, and 7/8 Viterbi
only; Rate 1/2 Sequential only; Rates 1/2 and 3/4 with
Viterbi and Reed-Solomon concatenated
•
QPSK—Rate 1; Rates 1/2, 3/4, and 7/8 Viterbi only; Rate
1/2 Sequential only; Rates 1/2 and 3/4 with Viterbi and
Reed-Solomon concatenated
Channel coding transmit interfaces
Text inside of brackets—[ ]—denotes features currently under development.
Channel encoding